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Visitor
Visitor
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Registered: ‎03-06-2018

virtex 6 ml 605 board mapping problem

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pls see the attachment.

Problems during programing:

1: Warning sign shown on map as shown in second screenshot.

2: The program has been succeeded, but the output is not shown by the led_2 as both the switches are ON (shown by screenshot).

 

pls reply as soon as possible

IMG_20180213_161208.jpg

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Xilinx Employee
Xilinx Employee
1,150 Views
Registered: ‎01-10-2012

Hi @harsh

 

First things First..

1. What is the warning message for the "Map"  ?the screen shot itself does not contain any info on the message generated by ISE, so cant say for sure if that warning can be ignored or not.

2. The first design looks straight forward, and Pin mapping seems to be correct, Assuming you are able to generate a valid bitstream

    (unless ISE has optimized away your entire logic..) the bit file should work

3. Why are using XSVF mode ? the Program succeeded only indicates that the tool has been able to generate the XSVF file,  this is  

    not same as programming the FPGA. 

   To program the FPGA you should use the bit File generated by your ISE project and program to the FPGA

   Please go through the "Assigning Configuration Files" section of  https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/ise_tutorial_ug695.pdf

 

4. The second design does not have correct mapping to a valid clock pin on your ML605, the Pin "AE22" is mapped to GPIO_LED_2 on ML605 & L21 is mapped to DIP_SW so you cant use this pin for output.

https://www.xilinx.com/support/documentation/boards_and_kits/ug534.pdf

 

 

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Xilinx Employee
Xilinx Employee
1,151 Views
Registered: ‎01-10-2012

Hi @harsh

 

First things First..

1. What is the warning message for the "Map"  ?the screen shot itself does not contain any info on the message generated by ISE, so cant say for sure if that warning can be ignored or not.

2. The first design looks straight forward, and Pin mapping seems to be correct, Assuming you are able to generate a valid bitstream

    (unless ISE has optimized away your entire logic..) the bit file should work

3. Why are using XSVF mode ? the Program succeeded only indicates that the tool has been able to generate the XSVF file,  this is  

    not same as programming the FPGA. 

   To program the FPGA you should use the bit File generated by your ISE project and program to the FPGA

   Please go through the "Assigning Configuration Files" section of  https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/ise_tutorial_ug695.pdf

 

4. The second design does not have correct mapping to a valid clock pin on your ML605, the Pin "AE22" is mapped to GPIO_LED_2 on ML605 & L21 is mapped to DIP_SW so you cant use this pin for output.

https://www.xilinx.com/support/documentation/boards_and_kits/ug534.pdf

 

 

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Visitor
Visitor
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Registered: ‎03-06-2018

we have ordered the 2Gb compact flash card. but it has been obsolete from the market. the vendor is saying that only 32 GB card is available.

  • can we insert the 32 Gb memory card of same dimensions? 
  • will it be compatible with this ML 605 virtex 6 board?
  • is it possible to use or program FPGA Virtex 6 without compact flash card?

Reply soon

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