We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for
Did you mean:
Observer
8,182 Views
Registered: ‎09-07-2009

## ABEL TO VHDL

hello,

how can I write ABEL Code like this:

BR.clk = CK;    // BR is a node register CK is a input pin

BR.ar = RSN;  // RSN is a input pin

in VHDL.

1 Solution

Accepted Solutions
Instructor
10,129 Views
Registered: ‎08-14-2007

## Re: ABEL TO VHDL

Not quite.  The D input part of the equation needs to be inside the process

block in order to happen at the clock edge.  In Abel you just use the := to

indicate at the clock edge.  In VHDL the assignment needs to take place

inside the elsif ...

Like:

process (CK, RSN)
begin
if RSN='1' then
BR <= '0';
elsif (CK'event and CK ='1') then

if BR(6) ='0' then BR <= BR+1;

else BR<="0000000"; -- in VHDL width of constant has to match width of BR

end if;
end process;

And:

process (BR(6), RSN)
begin
if RSN='1' then
UC <= '0';
elsif (BR(6)'event and BR(6) ='1') then
UC <= not UC;
end if;
end process;

-- Gabor
5 Replies
Instructor
8,177 Views
Registered: ‎08-14-2007

## Re: ABEL TO VHDL

You can find this in the language templates included in the ISE GUI.  What you're

describing in Abel is a flip-flop with an asynchronous clear input.  Normally you'd also

have an equation for the D input of your flip-flop.

-- Usage of Asynchronous resets may negatively impact FPGA resources
-- and timing. In general faster and smaller FPGA designs will
-- result from not using Asynchronous Resets. Please refer to
process (<clock>, <reset>)
begin
if <reset>='1' then
<output> <= '0';
elsif (<clock>'event and <clock>='1') then
<output> <= <input>;
end if;
end process;

In the above code, <output> could be replaced with BR,

<input> would be whatever goes to BR.d, <reset> could be RSN, and

<clock> would be CK.  Note that this code generates an active

high reset input.  RSN seems to imply an active low signal, but your

Abel code doesn't seem to bear this out.  The language templates

also have standard templates for flip-flops with asynchronous

presets and clock enables in all combinations of rising and falling

edge and active high or low inputs.

-- Gabor
Highlighted
Observer
8,173 Views
Registered: ‎09-07-2009

## Re: ABEL TO VHDL

If I understand your description the following Abel Code:

when !BR6 then BR := BR +1
else        BR := 0 ;
BR.CLK = CK;
BR.AR = RSN;
UC := !UC;
UC.CLK = BR6;
UC.AR = RSN;

is the same as this in VHDL

if BR(6) ='0' then BR <= BR+1;

elsif BR<='0';

process (CK, RSN)
begin
if RSN='1' then
BR <= '0';
elsif (CK'event and CK ='1') then
BR <= BR;
end if;
end process;

Tags (14)
Observer
8,172 Views
Registered: ‎09-07-2009

## Re: ABEL TO VHDL

sorry I forgot

UC <= NOT UC;

process (BR(6), RSN)
begin
if RSN='1' then
UC <= '0';
elsif (BR(6)'event and BR(6) ='1') then
UC <= UC;
end if;
end process;

Instructor
10,130 Views
Registered: ‎08-14-2007

## Re: ABEL TO VHDL

Not quite.  The D input part of the equation needs to be inside the process

block in order to happen at the clock edge.  In Abel you just use the := to

indicate at the clock edge.  In VHDL the assignment needs to take place

inside the elsif ...

Like:

process (CK, RSN)
begin
if RSN='1' then
BR <= '0';
elsif (CK'event and CK ='1') then

if BR(6) ='0' then BR <= BR+1;

else BR<="0000000"; -- in VHDL width of constant has to match width of BR

end if;
end process;

And:

process (BR(6), RSN)
begin
if RSN='1' then
UC <= '0';
elsif (BR(6)'event and BR(6) ='1') then
UC <= not UC;
end if;
end process;

-- Gabor
Observer
8,136 Views
Registered: ‎09-07-2009