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Registered: ‎09-15-2009

About block interleaver design

Dear All,
i am trying to implement a turbo encoder. I have developed RSC part of it. Now i am stuck in block interleaver ( new hardware architecture) code development. the new hardware architecture is loacated at link ( kindly help me in ressolving this issue. thanks
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Registered: ‎08-14-2007


If you have developed the RSC part, a block interleaver should be simple for you.

So what exactly is the problem? In the presented paper there's a block diagram of the 'new architecture' (Figure 2) that seems quite clear.



If the matrix stores whole data words or blocks of data words: 

You need a memory matrix and the write and read interfaces have to be able to shuffle the data around a little.

For convenience I would suggest to use a Dual Port RAM. Since RAM is a one dimensional vector of Datawords, you need some modulo adressing scheme that splits this vector into a matrix.  



If the matrix is just bit oriented:

You need 64 FFs to implement the matrix. (for 8 bit wordwith as in the paper, otherwise its wordwith^2 FFs)



The  only interesting part is the controll-LUT. Not the controll-LUT itself, it's simple, but what it implies:

Depending on the number of modes, the permutators become more or less complicated.


The most simple design would have only one mode, that reduces the permutators to simple wires.


So, where exactly are you stuck?


 have a nice synthesis?


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