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Visitor
Visitor
6,693 Views
Registered: ‎08-15-2012

Abram collision

Hi, 

 

I am using a dual port ram in my design but it is showing collisions when simulating the design because of the default address in two ports ( 0 ) , my question is can I use z-state as the default state in the design to avoid collision and how synthesize tool will  interpret  z  during synthesis ? I use the default value for the address to avoid latch , is there any alternative method to avoid this collision ?

 

Thanks in advance.

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Teacher
Teacher
6,666 Views
Registered: ‎09-09-2010

Re: Abram collision

> my question is can I use z-state as the default state in the design?

No. Not for synthesizeable designs.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Historian
Historian
6,658 Views
Registered: ‎02-25-2008

Re: Abram collision


@krayzzee wrote:

Hi, 

 

I am using a dual port ram in my design but it is showing collisions when simulating the design because of the default address in two ports ( 0 ) , my question is can I use z-state as the default state in the design to avoid collision and how synthesize tool will  interpret  z  during synthesis ? I use the default value for the address to avoid latch , is there any alternative method to avoid this collision ?

 

Thanks in advance.


Is this dual-port memory an external chip or are you implementing it using BRAM?

 

BRAM data buses are split into read and write data, so no tristating is necessary.

 

External devices typically have a bidirectional data bus, so both the memory itself and the thing to which it interfaces (in this case, the FPGA) must be capable of tristating their bus drivers to avoid collision. 

 

Doing this is easy. Your design should include an output enable signal, which, when asserted, allows the FPGA to drive the bus. When deasserted, the FPGA pins are tristated. The VHDL for the output is trivial:

 

    databus <= outdata when enable = '1' else (others => 'Z');

 

It is wise to design the logic such that the default value for enable is '0' so the output bus is tristate by default.

----------------------------Yes, I do this for a living.
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Visitor
Visitor
6,640 Views
Registered: ‎08-15-2012

Re: bram collision

 

I am implementing this design using BRAM  and I have chosen the default address as 0 the problem is that when I want to write to port B address 0 the port A address is 0 since the default address is 0 and it generates an error. How can I avoid this situation? I don't want to read from port A during this time .

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Historian
Historian
6,628 Views
Registered: ‎02-25-2008

Re: bram collision


@krayzzee wrote:

 

I am implementing this design using BRAM  and I have chosen the default address as 0 the problem is that when I want to write to port B address 0 the port A address is 0 since the default address is 0 and it generates an error. How can I avoid this situation? I don't want to read from port A during this time .


I'm not sure what this has to do with tristates, then.

 

you do realize that the BRAM is a true dual-port device, and each side has its own address and read and write data buses?

----------------------------Yes, I do this for a living.
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Visitor
Visitor
6,588 Views
Registered: ‎08-15-2012

Re: bram collision

Sorry , my questions is what would be the result if the addresses on  the two ports are same ? I think a collision will occur, now let me make it clear I don't want the port B to have the address 0 when Port A writes to address 0 by default port B is in read mode and has the address 0 . So I want a better default address for the port B to avoid this situation , every time when the logic executes it assigns 0 to the port b address if there is no read from port B, ie why it has the default address 0. simply how can I stop port B operations when I don't want to read from or write to it, my apprehension is that it will read from address 0 during each clock if the address remains constant. 

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Advisor
Advisor
6,569 Views
Registered: ‎10-05-2010

Re: bram collision

If you don't want the BRAM to read from port B, de-assert the ENB signal. From UG383:

 

EN[A|B]  When inactive no data is written to the block RAM and the output bus remains in its previous state. 

 

 

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