04-15-2014 01:58 AM
I'm working on a project of image processing, the design must detect edge, close edge, and calculate area between edge.
Someone already work on this project and write a design of 9000 lines, but the synthesis is too big for our target.
You can see result of synthesis for 2 diferents size of image, for full and part of design. The red case mean that XST can't synthesize because of limitation of my PC ram.
The design must work for a 576x720 image in full design but if we extrapolate for this case we would have near 1 000 000% of LUTs.
Do you think it's possible to optimise area and obtain a design which fit to my device?
And what is the technics for optimising?
The big part of this design is the closing of edge (by hysteresis and tree), there are many state machine for covering all specials cases in the algorithm
04-15-2014 02:01 AM
Which device and tools version are you using? If you are seeing overmapping, then it might result in error furing implementation. Can you explore targetting a larger device or family ?
04-15-2014 05:05 AM
I'm using spartan 3 xc3s1000 ft256 on xsa 3s1000 and Xstend v3 boards (from Xess). And I'm using ISE 14.1.
I can buy an other device but before I prefer trying reduce size of design it it's possible.
If I can't I think I will use processor because it 's a very sequential algorithm.