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Visitor
Posts: 11
Registered: ‎11-11-2008

# Barrel Shifter (Spartan 3A) Verilog

I am designing a 32bit risc processor and have a few questions.

I have a number of functional blocks written including the dual-port ram, the instruction decoding, logic section(and, or, xor, etc) of the ALU, etc.

I require a 32bit barrel shifter, that will shift left logical, shift right arithmetic, or rotate left or right, up to 31 positions.

Another requirement is to reverse a number of bits (from the left) for a count described by 5 bits. This may preclude me using the multipliers??

I think the 18x18 multipliers are capable of doing this. I know that I will have to convert my 5 bits (number of shifts) into a hot encoder, so that it becomes one operand of the multiplier (when shifting right). Will the same apply to shift left using divide or is there another way??

Alternately, the same could be built with 32x32 multiplexors, but this will use more CLB resources.

Can anyone lead me in the right direction as how to write the Verilog code for this ???

And, can the 18x18 multipliers do this or should I just use multiplexor logic???

Also, is there a free signed arithmetic IP ??? (add/sub, signed and  unsigned, 32bit)

Thanks

Instructor
Posts: 9,049
Registered: ‎08-14-2007

## Re: Barrel Shifter (Spartan 3A) Verilog

If you build a 32 x 33 multiplier (this would use 4 18x18 units) with 64 bits of output, you can do the full shift.

For shifting left, decode the 5 bits where 0 to 31 becomes 1, 2, 4, 8, ... 2^31.  Then use the low 32 bits of the

multiplier output.  For shifting right you would decode the 5 bitswhere 0 to 31 becomes 2^32, 2^31, ... 2.  Then

use the upper 32 bits of the multiplier as output.  For rotating, you would still need a multiplexer or to start

with a 64-bit multiplier where you take the value to be rotated and concatenate it with itself.

You may also want to consider using a multiplexer approach and seeing how this compares in terms of

combinatorial delay vs. using the multipliers.  Also note that either method can be pipelined if you need to

run at a higher clock rate.  By the way, the multiplexer approach can look like a tree of 4:1 muxes and

there may be more shared resources than you think, making the CLB usage reasonable.

-- Gabor
Visitor
Posts: 11
Registered: ‎11-11-2008

## Re: Barrel Shifter (Spartan 3A) Verilog

Thanks. Yes, I realise 4 18x18 multipliers will give me a barrel shifter, but not for what I require.

Since posting I have worked out the following:

One 32bit operand (the shift multiplier) is a 5bit hot encoded to 1 bit  active in a 32bit operand.

The other is a 64bit operand made up of 2 32bit operands. The lower and upper 32bits are described below.

All shifts are always left and requires 2 lots of 32 bit inputs. For rotates, they are both the same 32bit source. For shifts, the lower 32bits =0 for shift left, the upper 32bits =0 for shift right. For rotates with carry (my use requires the carry to be replicated) the lower or upper 32bits =c. For arithmetic shift right, the upper 32bits =bit31. Therefore in all cases the output is taken from the upper 32bit output.

Shift/rotates to the left shift the required number of bits (in a hot decode) left. Shift/rotates to the right shift (32 - the required number of bits) (in a hot decode) to the left.

I have another function which reverses a number of bits and clears the rest, and I can do this in a similar fashion.

However, I now have 96 inputs. This means I need 6 18x18 multipliers as I want to retain the speed.

Now I am not so sure that the multiplier is the right way to go.

My question still is how do I implement this in Verilog?

If I use multiplexers then I can state all cases, but this is a lot of code. Is there an easier way?

Instructor
Posts: 9,049
Registered: ‎08-14-2007

## Re: Barrel Shifter (Spartan 3A) Verilog

You can write the multiplexer as a loop.  Start by making a wire or reg with your 64-bit data in it.  Then the

loop just needs to do a part select on that vector.  For example inside a clocked always block you might write:

for (i = 0;i < 32;i = i + 1) if (sel == i) out_vec <= in_vec[i +: 32];

in_vec[i +: 32] says the same as in_vec[i+31:i], but the latter will not compile.

-- Gabor
Visitor
Posts: 11
Registered: ‎11-11-2008

## Re: Barrel Shifter (Spartan 3A) Verilog

Thanks very much. I don't understand in_vec[i+31:i] but I follow the rest.

If I use multiplexors I won't be performing the shift, so I will need to add a further step to mask the required bits. However, I will only have 32 inputs.

I can see what your code does, so I can write what I need. Thanks again :-)

Visitor
Posts: 11
Registered: ‎11-11-2008

## Re: Barrel Shifter (Spartan 3A) Verilog

I am looking for the IP for the 32x1 multiplexer. I think it is called MUX_32_1_SUBM.v or BUFE or BUFE_MUX_SLICE.pdf

I have the latest ISE v10.1.03 installed but it does not appear to be installed. I have also tried CoreGen.

Any ideas?

Instructor
Posts: 9,049
Registered: ‎08-14-2007

## Re: Barrel Shifter (Spartan 3A) Verilog

Mulitiplexers are usually inferred for HDL input.  In verilog you would make a case statement.  For a combinatorial

multiplexer you can use an always @* block like:

always @*

case (mux_sel)

0: mux_y = mux_in_0;

1: mux_y = mux_in_1;

. . .

31: mux_y = mux_in_ 31;

endcase

What I was pointing out in the for loop was that the part select in Verilog can only

be made using a single index.  for example in_vec[i+31:i] would seem to be the same as

in_vec[32:1] if i is 1, or in_vec[33:2] if i is 2, etc. but this does not compile.  The [i +: 32]

syntax says in effect always take 32 bits starting at i and working up.  I understand

that the dual-index addressing may be fixed in System Verilog.  The loop I wrote

was intended to do a shift function as an example of inferring a multiplexer using

a loop with part selects rather than a case statement with individial inputs.

Regards,

Gabor

-- Gabor
Visitor
Posts: 11
Registered: ‎11-11-2008

## Re: Barrel Shifter (Spartan 3A) Verilog

Thanks Gabor,

I understand your statements in verilog. I am fairly new to verilog so didn't realise that I could do what you have suggested.

The reason I asked about the multiplexer IP is from what I read, the Xilinx implementation will make better use of the CLBs. I guess I will just try the verilog statements along the lines you have suggested and see what the ISE utilises.

I think it will be more efficient to just do a 32x1 mux to rotate. I will then either modify the input 32bits or output 32bits to mask the bits which must be "0" or "1" as a separate piece of logic as I believe this will use less logic and only add 1 level in delay. Perhaps I can also use this section to perform the and/or/xor and the reverse section as well. For this I may be able to use CLUT (lookup).

Thanks again for your help :-)  I'll post my results.

Visitor
Posts: 11
Registered: ‎11-11-2008

## Re: Barrel Shifter (Spartan 3A) Verilog

I tried

for (i = 0;i < 32;i = i + 1) if (sel == i) out_vec <= in_vec[i +: 32];

but could not get it to work.

I coded the case statement for a 32x32 multiplexer, but it compiled to 92 slices. I cannot find the datasheet for the BUFE_slice multiplexer referred to in the IP section. However, from documents I have, it should compile to 64 slices.

So my question is this... Where do I get the IP for the Xilinx BUFE_Slice ?

My design for the complete multiplexer/shifter/rotator takes 348 slices, so I am sure the Xilinx implementation will greatly improve this.

Instructor
Posts: 9,049
Registered: ‎08-14-2007

## Re: Barrel Shifter (Spartan 3A) Verilog

It is my understanding that the BUFE_Slice multiplexer uses internal tristate buses that are

no longer available on parts after Spartan 2.

-- Gabor