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Observer diegoroman17
Observer
23,578 Views
Registered: ‎04-14-2012

Best practice with Clock divider in FPGA

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Hi everyone,

I am beginning at the world of FPGA and the VHDL. I have wrote code in VHDL y tested with the basic concepts of FLIP-FLOPs, Models, Sequencies, FSMs, etc. Now I am viewing the manage Clock within FPGAs and I want test with a blink led. I have in my board a clock input signal of 40MHz and want divide this to 1Hz, 10Hz, etc. I have tried with Clocking Wizard but it does not posible because the frequency output is very small. I have thought do it with counters that divide my input clock, also I think in use the Clocking Wizard for divide my clock to 5Mhz and after to use counters. Exist various options for this task, my question is, which is the better option considering the performance, resources, etc, for do this task?

 

Thanks.

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1 Solution

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Teacher eteam00
Teacher
32,958 Views
Registered: ‎07-21-2009

Re: Best practice with Clock divider in FPGA

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In every design I have ever seen, the signal used as "clock" or "SCL" in an I2C channel is generated from a state machine running at some higher frequency with some other 'master' system clock.

 

For purposes of FPGA design, the SCL signal (as either input or output) is *not* a clock.  It is nothing more than a timing reference for the SDA (data) signal, for all the devices connected to the I2C channel.

 

When desiging FPGA logic, a clock signal is (generally speaking) a constantly running clock.  The SCL signal of an I2C controller interface is a clock in the context of I2C, but is simply another formed handshake signal in the context of FPGA logic design.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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7 Replies
Teacher eteam00
Teacher
23,576 Views
Registered: ‎07-21-2009

Re: Best practice with Clock divider in FPGA

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Use a multi-bit synchronous counter to divide the clock.  Then you can use either counter bits to directly drive the LEDs, or you can decode the counter bits to perform attention-getting functions (for example:  gradual cycling between dim and bright, a walking light pattern, etc.).

 

You should use (or need) only one clock.  All functions should be decoded from the counter bits.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Observer diegoroman17
Observer
23,572 Views
Registered: ‎04-14-2012

Re: Best practice with Clock divider in FPGA

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Then, When is neccesary use the clocking wizard? and when is neccesary use a hybrid between cloking wizard and counters? Could give me any example, please?

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Teacher eteam00
Teacher
23,568 Views
Registered: ‎07-21-2009

Re: Best practice with Clock divider in FPGA

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The Clocking Wizard is a user-friendly menu-driven interface for selecting clock generation circuitry (PLL, DLL), synthesis mode, input configuration and output configuration.  The result is a set of attributes attached to an instance of PLL or DLL or DCM which perform the functions you specify.

In other words, the Clocking Wizard simplifies the instantiation of a DCM/DLL/PLL clock generator.

The Clocking Wizard cannot provide features which are not realisable with the actual PLL/DLL/DCM.  Hence, clock division for the purposes of driving LEDs is *not* an intended Clocking Wizard function.

 

Is this the sort of answer for which you were looking?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Observer diegoroman17
Observer
23,548 Views
Registered: ‎04-14-2012

Re: Best practice with Clock divider in FPGA

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Yes, This is the response, very good explanation. Thanks. Now I have other question over the same theme. Ok I understand that clocking wizard is not for driven a led, but if I want generate a clock of 400kHz for a logic system, for example I2C of low speed, how I can do it? Is correct do it with counters? the signal clock is correctly routed in high speed lines within FPGA with counters? Sorry for the questions, but I try understand the concepts in deep.

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Teacher eteam00
Teacher
32,959 Views
Registered: ‎07-21-2009

Re: Best practice with Clock divider in FPGA

Jump to solution

In every design I have ever seen, the signal used as "clock" or "SCL" in an I2C channel is generated from a state machine running at some higher frequency with some other 'master' system clock.

 

For purposes of FPGA design, the SCL signal (as either input or output) is *not* a clock.  It is nothing more than a timing reference for the SDA (data) signal, for all the devices connected to the I2C channel.

 

When desiging FPGA logic, a clock signal is (generally speaking) a constantly running clock.  The SCL signal of an I2C controller interface is a clock in the context of I2C, but is simply another formed handshake signal in the context of FPGA logic design.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

View solution in original post

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Observer diegoroman17
Observer
23,524 Views
Registered: ‎04-14-2012

Re: Best practice with Clock divider in FPGA

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Perfect. Now I understand a few more over Clock theme, but there is a large way for learn VHDL and FPGA. Thanks for help me Bob.

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5,151 Views
Registered: ‎10-24-2018

Re: Best practice with Clock divider in FPGA

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can u give me the report of that clock divider and also source code and testbench

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