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Adventurer
Adventurer
9,312 Views
Registered: ‎02-12-2015

Camera Link Receiver signal alignment

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Hi,

 

I've got a camera link receiver running on a Zync board but am having trouble figuring out the individual signal assignments.

 

My design is based on the ISERDESE1 primitive using SDR.

 

I've scoped my clock signal and the clock division seems good. I've had to invert my outputs from the SERDES blocks to get them looking as expected.

 

I've set my camera to free running mode, outputting a black test image so I could verify LVAL and DVAL. The problem is I see signals matching the expected LVAL on RxOuts 20,19 and 18 (see attached scope shot). I see nothing on the other signals as expected but do see what look likes data on other signals when I change the test image. I expected to see LVAL and DVAL on 24 and 26.

 

I took my code from another thread on here which I cannot find anymore, but from reading around, the system needs to settle on a clock pattern of 1100011. When I inverted my outputs I now look for 0011100 pattern which I find and lock to. See below for the state machine used to lock the signal:

 

-- Alignment state machine
process (reset, clk_bufg)
begin
if reset = '1' then
state <= 0;
locked_int <= '0';
psen <= '0';
elsif rising_edge(clk_bufg) then
-- Reset ISERDES modules
if state = 0 then
state <= 1;
locked_int <= '0';
psen <= '0';
iserdes_rst <= '1';
elsif state = 1 then
state <= 2;
counter <= (others => '0');
iserdes_rst <= '0';
-- Wait for ISERDES outputs to settle
elsif state = 2 then
counter <= counter + 1;
if counter(3) = '1' then
counter <= (others => '0');
stable_counter <= (others => '0');
clclk_ref <= clclk;
state <= 3;
end if;
-- Stability check
elsif state = 3 then
counter <= counter + 1;
if clclk_ref /= clclk then
-- Not stable, advance
psen <= '1';
psincdec <= '1';
stable_counter <= (others => '0');
state <= 4;
elsif counter(15) = '1' then
-- Stable, increment stable count
stable_counter <= stable_counter + 1;
-- Has signal been stable for 32 phases?
if stable_counter(5) = '1' then
-- Signal is stable, are we at proper camera link clock phase?
if clclk = "0011100" then
counter <= (others => '0');
state <= 5;
-- If wrong phase, keep advancing
else
psen <= '1';
psincdec <= '1';
stable_counter <= (others => '0');
state <= 4;
end if;
else
-- We haven't tested 32 stable phases, advance to next phase
psen <= '1';
psincdec <= '1';
state <= 4;
end if;
end if;
-- Wait for phase shift to complete
elsif state = 4 then
psen <= '0';
if psdone = '1' then
counter <= (others => '0');
clclk_ref <= clclk;
state <= 3;
end if;
-- We're at the correct cameralink clock phase, advance until unstable
elsif state = 5 then
counter <= counter + 1;
if clclk /= "0011100" then
counter <= (others => '0');
stable_counter <= (others => '0');
state <= 7;
elsif counter(15) = '1' then
-- Stable, keep advancing
psen <= '1';
psincdec <= '1';
state <= 6;
end if;
-- Wait for phase shift to complete
elsif state = 6 then
psen <= '0';
if psdone = '1' then
counter <= (others => '0');
state <= 5;
end if;
-- We're at the correct cameralink clock phase, reverse until unstable
elsif state = 7 then
counter <= counter + 1;
-- Unstable?
if clclk /= "0011100" then
-- If we've already been through a large stable area, then we're at the leading edge of the stable range
if stable_counter > 31 then
state <= 9;
counter <= (others => '0');
-- Otherwise, we need to keep reversing until we get into the large stable range
else
psen <= '1';
psincdec <= '0';
stable_counter <= (others => '0');
state <= 8;
end if;
elsif counter(15) = '1' then
-- Stable, increment stable count and reverse another step
stable_counter <= stable_counter + 1;
psen <= '1';
psincdec <= '0';
state <= 8;
end if;
-- Wait for phase shift to complete
elsif state = 8 then
psen <= '0';
if psdone = '1' then
counter <= (others => '0');
state <= 7;
end if;
-- Advance back to middle of stable range
elsif state = 9 then
counter <= counter + 1;
if counter(14 downto 0) = stable_counter(15 downto 1) then
state <= 11;
else
psen <= '1';
psincdec <= '1';
state <= 10;
end if;
-- Wait for phase shift to complete
elsif state = 10 then
psen <= '0';
if psdone = '1' then
state <= 9;
end if;
-- Alignment complete
elsif state = 11 then
locked_int <= '1';
end if;
end if;
end process;

 

Any ideas / comments I'd be very grateful.

 

Thanks in advance, Marc.

WP_20150715_001.jpg
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Adventurer
Adventurer
17,304 Views
Registered: ‎02-12-2015

Re: Camera Link Receiver signal alignment

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This post has the solution -

http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Cameralink-on-Virtex6/td-p/178232

I do not understand where the bit mapping comes from but it works! If anyone could explain I would be grateful!



The code creates the output signal as follows:

RX_DATA <= "000000" & d(19 downto 18) & d(26 downto 25) & d(17 downto 12) & d(24 downto 23) & d(11 downto 6) & d(22 downto 21) & d(5 downto 0);
FVAL <= RX_DATA(25);
LVAL <= RX_DATA(24);

DATA <= RX_DATA(23 downto 0);

View solution in original post

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Adventurer
Adventurer
17,305 Views
Registered: ‎02-12-2015

Re: Camera Link Receiver signal alignment

Jump to solution
This post has the solution -

http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Cameralink-on-Virtex6/td-p/178232

I do not understand where the bit mapping comes from but it works! If anyone could explain I would be grateful!



The code creates the output signal as follows:

RX_DATA <= "000000" & d(19 downto 18) & d(26 downto 25) & d(17 downto 12) & d(24 downto 23) & d(11 downto 6) & d(22 downto 21) & d(5 downto 0);
FVAL <= RX_DATA(25);
LVAL <= RX_DATA(24);

DATA <= RX_DATA(23 downto 0);

View solution in original post

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Historian
Historian
9,167 Views
Registered: ‎02-25-2008

Re: Camera Link Receiver signal alignment

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@marc.pearson wrote:
This post has the solution -

http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Cameralink-on-Virtex6/td-p/178232

I do not understand where the bit mapping comes from but it works! If anyone could explain I would be grateful!

It comes from the Camera Link spec. It's also found in the data sheet for the TI DS90CR287 Camera Link transmitter.

----------------------------Yes, I do this for a living.
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Adventurer
Adventurer
9,150 Views
Registered: ‎02-12-2015

Re: Camera Link Receiver signal alignment

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The camera link spec states that my first pixel should be constructed from bits Rx0,1,2,3,4,6,27,5 ?

I orginally mapped RX directly from the deserialized X0, X1, X2, X3 signals i.e X0 provided Rx0-6, X1 - Rx7-13, X2 - Rx14-20, X3 - Rx21-27

but the above solution does not - I can't find documentation that maps the deserialized bits to Rx0-27 ?

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Historian
Historian
9,118 Views
Registered: ‎02-25-2008

Re: Camera Link Receiver signal alignment

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marc.pearson wrote:
The camera link spec states that my first pixel should be constructed from bits Rx0,1,2,3,4,6,27,5 ?

I orginally mapped RX directly from the deserialized X0, X1, X2, X3 signals i.e X0 provided Rx0-6, X1 - Rx7-13, X2 - Rx14-20, X3 - Rx21-27

but the above solution does not - I can't find documentation that maps the deserialized bits to Rx0-27 ?


DId you RTF TI Data sheet? It's all there.

----------------------------Yes, I do this for a living.
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