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Visitor
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Registered: ‎09-25-2015

Clk 2.304 MHz

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hi

plz ,how to make Clk 2.304MHz  ? input clock is 24 MHz...

thanks

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Guide
Guide
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Registered: ‎01-23-2009

Re: Clk 2.304 MHz

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Yes.

 

You can use the CLKFX output of the MMCM using a multiply of 12 and a divide of 5 to get 57.6MHz. With these multipliers and dividers, though, the jitter isn't expected to be particularly great...

 

To get from 57.6 to 2.304, you need to divide by 25.

 

You don't tell us what you want to do with this frequency, so its hard to say how to use it within the FPGA. If it is for clocking internal logic, you have two choices

  - clock all the logic on the 57.6MHz clock (on a BUFG) and only enable the updates of the flip-flops on every 25th clock

     - use a counter that counts from 24 to 0, and use the 0 condition as the enable for all the flip-flops on the 2.304Mhz domain

  - use the 57.6MHz clock (on a BUFG) to generate the same counter and use a BUFGCE to generate the 2.304MHz clock

     - the input of the BUFGCE also comes directly from the CLKFX output of the DCM (so the same signal as the input to the BUFG)

     - the CE of the BUFGCE is the 0 count of your counter

 

Both of these will be fine for internal logic, but neither generates a true "clock" - the BUFGCE's output is not a square wave, but a pulse every 25 clocks (where each pulse is 1/2 of the period of the 57.6MHz clock). For internal clocking this is perfectly fine (as long as you don't use the falling edge of the clock). For forwarding, though, you would have to generate a square wave using the 57.6MHz clock using an ODDR - have the output high for 12.5 clocks and low for 12.5 clocks; have {D1,D2} = 2'b11 for 12 cycles, {D1,D2} = 2'b10 for one cycle, {D1,D2} =2'b00 for 12 cycles  - and repeat.

 

Avrum

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Scholar
Scholar
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Registered: ‎02-27-2008

Re: Clk 2.304 MHz

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m,

 

If you require exactly 2.304 MHz, then you should probably just get an oscillator with a frequency that is easy to use by simple division.

 

Synthesizing 2.304 digitally can be done with a direct digital frequency synthesizer (DDFS), but there will be jitter at the clock frequency (24 MHz unit interval, ~ 40ns).  That may not be ideal, and the frequency out will be off by the number of bits in the accumulator.  Now 48 bits is +/- 3.5E-15, so getting close enough to be practical is possible, and very easy to do in a FPGA as the DSP48 may be arranged as a DDFS easily.

 

The jitter may be filtered out by folloing the DDFS with a PLL if needed.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor
Visitor
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Registered: ‎09-25-2015

Re: Clk 2.304 MHz

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thanks,

i make 57.6 MHz with DCM,then make 2.304 MHz with counter,is it true?

if this is true,how do i move to clock network?

 

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Highlighted
Guide
Guide
16,394 Views
Registered: ‎01-23-2009

Re: Clk 2.304 MHz

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Yes.

 

You can use the CLKFX output of the MMCM using a multiply of 12 and a divide of 5 to get 57.6MHz. With these multipliers and dividers, though, the jitter isn't expected to be particularly great...

 

To get from 57.6 to 2.304, you need to divide by 25.

 

You don't tell us what you want to do with this frequency, so its hard to say how to use it within the FPGA. If it is for clocking internal logic, you have two choices

  - clock all the logic on the 57.6MHz clock (on a BUFG) and only enable the updates of the flip-flops on every 25th clock

     - use a counter that counts from 24 to 0, and use the 0 condition as the enable for all the flip-flops on the 2.304Mhz domain

  - use the 57.6MHz clock (on a BUFG) to generate the same counter and use a BUFGCE to generate the 2.304MHz clock

     - the input of the BUFGCE also comes directly from the CLKFX output of the DCM (so the same signal as the input to the BUFG)

     - the CE of the BUFGCE is the 0 count of your counter

 

Both of these will be fine for internal logic, but neither generates a true "clock" - the BUFGCE's output is not a square wave, but a pulse every 25 clocks (where each pulse is 1/2 of the period of the 57.6MHz clock). For internal clocking this is perfectly fine (as long as you don't use the falling edge of the clock). For forwarding, though, you would have to generate a square wave using the 57.6MHz clock using an ODDR - have the output high for 12.5 clocks and low for 12.5 clocks; have {D1,D2} = 2'b11 for 12 cycles, {D1,D2} = 2'b10 for one cycle, {D1,D2} =2'b00 for 12 cycles  - and repeat.

 

Avrum

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Teacher
Teacher
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Registered: ‎03-31-2012

Re: Clk 2.304 MHz

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You can use a PLL to generate a 172.8 MHz clock from 24 MHz (*36/5 or you can let the clock wizard to select a better fractional multiply-divide ratio to get a more optimal VCO clock) and then it's a simple divide by 75 to get 2.304 MHz which you can generate with a clock enable instead of actually generating a 2.304 MHz. Ie you take 172.8 MHz clock and generate a clock enable for the downstream circuit once every 75 cycles.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Visitor
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Registered: ‎09-25-2015

Re: Clk 2.304 MHz

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i attach my code and simulation.Behavioral simulation is true but,post_route isnt true.

please advise me,how to write my code..

thanks.

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