09-26-2012 06:56 AM
being not so familiar with (SI and FPGA-related) physical restrictions conserning clocks, I have a question about clocking the GTX Quad on the Xilinx Kintex-7 KC705 board.
The board has Si570 ("Si570 3.3V LVDS I2C Programmable Oscillator") routed to:
NET USER_CLOCK_P LOC = K28 | IOSTANDARD=LVDS_25; # Bank 15 VCCO - VCC2V5_FPGA - IO_L13P_T2_MRCC_15
NET USER_CLOCK_N LOC = K29 | IOSTANDARD=LVDS_25; # Bank 15 VCCO - VCC2V5_FPGA - IO_L13N_T2_MRCC_15
On the same bank there are signals routed to SMA-connectors on the board (for clock input):
NET USER_SMA_CLOCK_P LOC = L25 | IOSTANDARD=LVDS_25; # Bank 15 VCCO - VCC2V5_FPGA - IO_L12P_T1_MRCC_AD5P_15
NET USER_SMA_CLOCK_N LOC = K25 | IOSTANDARD=LVDS_25; # Bank 15 VCCO - VCC2V5_FPGA - IO_L12N_T1_MRCC_AD5N_15
Am I able to drive the clock signal out to these SMA-connectors and connect them to the SMA GTX clock in SMA connectors on the board (wired to GTX Quad bank 117)? If not, why (SI / jitter related?)?
The Si5326 jitter attenuator on the board is maybe targeted for this kind of use (routed to the GTX Quad 116)? But I suppose there isn't a easy way to program it..? And also that it doesn't power on to some default state that would be usable, or?
I'm trying to get a 150MHz clock for Aurora core for SFP (on the GTX Quad 117) with Aurora IP Core connection .
KC705 User Guide:
09-26-2012 09:47 AM
Ah, the Kintex-7 GTX Quad's have a clock input pin named GTGREFCLK, which is possible to be driven by FPGA logic:
GTGREFCLK / In / Clock / Reference clock generated by the internal FPGA logic. / This input is reserved for internal testing purposes only.
I suppose this is supported by the ISE? Is it better to route the Si570's clock through the fabric to this pin, or through the SMA-connectors? Or am I doomed regardless?