01-23-2015 06:31 PM
I'm trying to connect the AXIS 10GE MAC to Zynq in Vivado. The manuals aren't much help as they aren't specific to the Zynq AXI ports. I'm trying to use the AXI DMA, as it is one of the few modules that convert from stream (10GE output) to AXI memory mapped (Zynq input), but I'm not sure I'm getting it right. I've attached a screen shot of part of my Vivado block diagram. The 10GE block is above the attachment. There are AXIS interconnects for Tx, Rx, Command and Status. Is there a Vivado reference design that someone can point me toward?
01-25-2015 04:53 PM
What you are trying to accomplish is not an easy task. Hooking things up to get both TX and RX working is one thing, getting anywhere near 10G throughput is another.
This whitepaper might be helpful to you: http://www.xilinx.com/support/documentation/white_papers/wp459-data-mover-IP-zynq.pdf
You will want to carefully plan how the 10GE RX is going to deliver received packets to the CPU. Are you setting aside ring buffer space in the main memory?
01-26-2015 11:43 AM
Thank you for the reference. I'm sure it will help a lot.
Luckily for us, we don't need the entire 10G bitrate. Two or three times 1G would work for us. Also, the critical direction for us is Tx, not Rx, as we have a lot of data to ship out, but only control and 2nd stage loading to receive.
I was thinking of using the scatter/gather queues in the AXI DMA to help with throughput, but I will certainly look at what the white paper recommends. I would also welcome any suggestions from you and the Forum.
Again, thanks for the reference!
11-30-2015 12:16 PM
Asking the question again after 10 months.
Is there a Zynq reference design for 10G Ethernet?