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Anonymous
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Delay Locked Loop Xilinx article - question

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Hi all! I came across a nice Xilinx article about delay locked loops, and have a small question about the practical implementation of it - as compared with the block diagram given on page 2 of the article (attached).

 

I can see that the simplest delay locked loop example involves an input clock (or source clock), and a controllable delay line is used to produce another clock signal that is "in-phase" with the input clock. The produced "in-phase" clock signal is then distributable over the clock distribution network.

 

Working toward my question, I briefly start out with a short description of the delay locked loop. Regarding Figure 1 of the article, which shows a delay locked loop diagram, the feedback signal (labelled as "CLKFB") is meant to be compared with the input clock signal ("CLKIN"). The loop action is meant to minimise the phase difference between the CLKFB and the CLKIN signal at the inputs to the phase comparator.

 

I assume that output of the variable delay line is connected to the clock distribution network via a transmission line of a finite length (as shown in red colour of my second file attachment). And the clock distribution network is then connected back to the phase comparator input via another transmission line having a significant finite length.

 

My quick question is - the basic block diagram of a delay locked system (Figure 1 of article) doesn't appear to take those finite length transmission lines into consideration. So, for relatively high frequency clock signals, will the presence of interconnecting transmission lines prevent a delay locked system from achieving the desired objective of synchronising the clock distribution network signal and the distant (input clock) signal?

 

So, basically, what I'm trying to convey is (referring to my jpg image) - reference point B and reference point C are along the same connecting transmission line. However, they are physically at different points, so while signals at "A" and "B" might become phase-locked, I was thinking that the signal at "C" will not be the same phase as "A" and "B" (even when "A" and "B" have become phase-locked).

 

I realise that I must be over-looking something important, so that's why I decided to ask about it. I've thought about it a lot, and don't quite understand the real situation. Thanks for any advice and comments in advance!

 

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delay_locked_loop.jpg
xilinx_delaylockedloop.jpg
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drjohnsmith
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Registered: ‎07-09-2009

Balancing the two routes back to the comparitor is what has been done in the chips.

 

Its a mixture of Xilinx's chip designers, and the tools,

 

you have to do nothing,

 

As an extreme if the clock is constant, then the transmission path delays , provided they are both the same, do not matter.

   

the delay could be 1 ps or 100 ns, 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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avrumw
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Registered: ‎01-23-2009

So, first - in your drawing you write "Voltage control" on the control block.  In most/many DLLs the control is completely digital - it does not work by varying the voltage on the delay elements, but instead varies the number of delay elements in the chain used to obtain a particular delay. The DCMs in older Xilinx devices are pure digital DLLs (newer devices use PLLs and MMCMs, which are analog, and operate differently - although the behavior of the CLKFB for phase matching is similar).

 

But to answer your question, you have to understand how the clock distribution networks in an FPGA work. In the FPGA there are pre-routed clock distribution networks of different types - I will focus on the "global clock" network in older FPGAs (7-series and before - UltraScale is different).

 

Each FPGA has a finite number of global clock distribution networks - in most families and devices there are 32 of them. Each of the global distribution networks is fed by one BUFG/BUGCE/BUFGMUX/BUFGCTRL, which is usually located in the center of the FPGA die. From there, the network fans out to every clocked element on the entire FPGA die (each clocked element can select which global or other clock network to use for its clock input). While the time to traverse this network (called insertion delay) may be fairly long, In order to operate as a synchronous system, the global network must be "skew balanced" - the arrival time of the clock at the "closest" and "farthest" node must be within a reasonable tolerance (called the clock skew).

 

The CLKFB input of an DCM is a clock endpoint. Like all other clock endpoints, it receives its signal from the global clock network. As such, the arrival time at the CLKFB input of the DCM is skew balanced with all other endpoints of the clock. So if the DCM phase matches the CLKFB input to the CLKIN input, and the CLKFB input is skew balanced with all other clock endpoints, then the clock arrives at all endpoints at the same time as the CLKIN, plus or minus the clock skew of the network and the CLKIN/CLKFB phase tolerance of the DCM.

 

Avrum

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drjohnsmith
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Registered: ‎07-09-2009

Your right , sort off.

 

The question to ask is what delays are the DLLs trying to compensate for .

 

Traditionally, the input pin and "the buffer" for the clock had a significant delay 

 

     The DLL's were originally used to null out this clock input pin delay,

           this used to be a big problem.

 

               and there was a 'war' between PLLs and DLL's, and marketing sheets on how to use them.

                  which is I think where the article you have came from.

 

Trying to apply more than that level of detail to much newer and MUCH bigger parts might be  taking the article to far

 

 

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Anonymous
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Thanks, Avrnumw, for your help and very kind information. I will write those details down.

I'm still trying to understand the situation though. Let me explain. I mentioned that the clock feedback signal CLKFB needs to be connected to the phase comparator via a real (physical) transmission line.

 

So, when delay lock is achieved, the signals at "A" and "B" will be in-phase. However, due to the finite length of the connecting transmission line between "B" and "C", the phase of the signal at "C" will not be the same as the phase at "A" and "B".

 

I can understand situations where the clock frequency is extremely low, or where the wavelength of the clock signal is many many times greater than the length of the transmission line, in which case the phase introduced by the transmission line can be negligible. However, at relatively high frequency, the extra phase introduced by connecting transmission lines can be significant.

 

So, for GHz frequency clock signals, it appears that the delay locked loop system won't be able to work as intended. That is, the aim is to get the phase of the signal at "C" to be virtually the same as the phase at "A" (and "B"). However, the significant length of connecting transmission line between the point "C" and point "B" doesn't seem to be taken into account. So it just appears that the DLL system won't be able to automatically get signals at point "C" and point "B" to be in-phase.

 

I'm still assuming I may have the wrong interpretation of the problem at hand though. My assumption is that the signal at point "C" needs to be automatically conditioned to become in-phase with the input clock signal at point "A". But the transmission line between "B" and "C" is a problem. Thanks again Avrnum! Kenny.

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Anonymous
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Hi Dr John! Love the dalek avatar by the way! Thanks for your reply and comments!

The delay locked loop system appear to be extremely powerful, but their usage sometimes confuses me.

 

I was thinking that at relatively low frequency, where the interconnecting transmission lines between the phase comparator and feedback "point" doesn't introduce any extra significant phase shift, then the delay locked loop system would help to take care of the rest of the phase (to be compensated for), such as the phase shift between the variable delay line and the reference plane at some other 'clock input'.

 

But it just seems to me that at relatively high frequency, such as GHz frequency, these extra interconnecting lines (that are needed to physically create a delay locked loop circuit) start getting in the way of things.

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drjohnsmith
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Dont take the diagram to litraly

  

What about if the IC designers had set the lengths of both lines into the comparitor to the same delay ?

 

Would the propagation delay down the lines matter then ?

 

At the end of the day,

   the tools tell you all you need to know.

 

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avrumw
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Please re-read my previous post.

 

The CLKFB is fed by the clock distribution network, and all endpoint of the clock distribution network are skew balanced with eachother.

 

Move your "C" to be the end of the clock distribution network (not the beginning) - this means that the point C is the arrival at any flip-flop in the design (including an IOB FF) - or at least within the clock skew of the clock network. For "important" flip-flops within the clock network (notably the IOB FFs) this clock skew is balanced to be within a few 100 (or even a few 10) picoseconds.

 

So now your path from the DCM to C is skew balance with the path from the DCM to B - the lengths of these paths is balanced. So since point A and B are kept in phase, and point B and C are skew balanced, all flip-flops now receive a clock that is in phase with clock A.

 

Second, no one is talking about GHz frequencies. Neither the DCMs nor the clock distribution networks in devices that have DCMs (Virtex-5, Spartan-6) can run at those frequencies - the maximum is 550MHz in a V5 at the fastest speed grade and significantly less for the Spartan-6.

 

Furthermore, the phase matching of clocked elements to the CLKIN is only critical for input/output interfaces (the phase of CLKIN is irrelevant to paths that start and end on the internal clock - only the clock skew matters). The practical limits to statically capturing input interfaces is around 500Mbps (which is usually done DDR - so 250MHz).

 

So, for these applications and at the frequencies that matter in an FPGA, the skew matching of the CLKFB path with the clock distribution path is adequate.

 

Avrum

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Anonymous
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dr JS - thanks for your advice about the diagram. To answer the question of what happens if both lines of the comparator be set to the same length (and therefore same phase delay), I think that the issue would be addressed (rectified) for that case. Thanks dr JS!

 

Avrnum also mentioned something important. The frequency of operation is not as high as I had assumed it to be. I had incorrectly assumed that the signal wavelengths were in the order of the lengths of interconnecting transmission lines. But it looks like the clock signal wavelengths are many times the length of any internal transmission line, such that phase delay introduced by internal transmission lines could be considered insignificant.

 

In FPGA, it looks like delay due to transmission lines don't impact the objective of the delay locked loop system too much.

 

Thanks again drJS!

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Anonymous
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Hi Avrnum, thanks very much for putting me on the right path! Your comment about the frequency of operation was incredibly helpful, as I had incorrectly assumed that the frequency was much higher than the real case. Everything is clear now. I've written down the notes you and dr JS very kindly provided. The details you gave were tremendously helpful Avrnum! Thanks very much for your time to show me (and very highly likely other people) some important aspects of delay locked loop systems, and clock distribution network in FPGAs. Genuinely appreciated. Thanks once again!!

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avrumw
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such that phase delay introduced by internal transmission lines could be considered insignificant

 

Careful - I never said that...

 

The clock distribution networks in an FPGA (and even in an ASIC, for that matter) are not merely wires (or transmission lines); they are buffered at various different stages. So the propagation of these networks is not merely the transmission line delays (at a significant percentage of the speed of light), but delay through a number of active interconnects and buffers.

 

The clock insertion delay of an FPGA can be well into the several nanosecond range. Even at the frequencies of a DLL, these are quite significant; a large Virtex-5 can do clocks > 500MHz (so 2ns period), but the clock insertion can be more than 3ns - so it is essential for the DLL to compensate for this insertion delay - and do it quite accurately - in order to be able to implement high speed input and output interfaces.

 

And they do compensate for them using the mechanism I described; by having the CLKFB path match the clock insertion path to any other (important) clocked element.

 

Avrum

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Anonymous
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Hi again Avrnum!

 

Thanks for adding more to this topic. Looks like I've assumed incorrectly again - in that it appears that transmission line delay as well as buffering delay won't be insignificant.

 

What I've done is - I've modified my diagram, and have now placed the point "C" at the end of the clock distribution network. So I'm back to square 1 again. Due to transmission line delay (since connecting lines are needed to complete the delay locked loop system), and due to the mentioned extra delays, like clock buffering...... is it true that these added delays will prevent the delay locked loop system from fulfilling the aim of making the phase of the signal at "C" to become the same as "A" and "B"?

delay_locked_loop1.jpg
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avrumw
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The clock distribution network is a network - it is a set of interconnects that reaches ALL clock endpoint in a balanced fashion. So every endpoint of the network INCLUDING THE FEEDBACK TO THE DLL are balanced. Therefore the arc C->B doesn't exist - it is part of the clock distribution network.

 

Avrum

Anonymous
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Avrnum, I see. Thanks.

 

However, the "end-point(s)" of the clock distribution network need to "physically" connect back to the input of the phase comparator.

 

So a transmission line must be involved. The issue here is .... where are the planes of reference? I needed to show a diagram to ensure that I understand the situation properly. You mentioned the arc "C-B" doesn't exist. The arc C-B is only to convey that there is an introduced delay between a "slave" clock signal point and the immediate feedback input (at point "B" of the comparator). The introduced delay exists because we need to physically connect a "slave" clock point (or end-point of the clock distribution network... eg. point "C") to the input of the phase comparator at point "B" (via a transmission line). I'm trying to understand how this extra introduced delay (phase) is taken into account, or removed.

 

Dr JS mentioned a possible solution, such as to purposely fabricate a transmission line (to be placed between the reference clock "CLKIN" and the input "A" of the phase comparator), and this transmission line needs to be approximately the same length as the "feedback" transmission line.

 

Would this technique of designing equal length transmission lines be used in practice?

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drjohnsmith
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Balancing the two routes back to the comparitor is what has been done in the chips.

 

Its a mixture of Xilinx's chip designers, and the tools,

 

you have to do nothing,

 

As an extreme if the clock is constant, then the transmission path delays , provided they are both the same, do not matter.

   

the delay could be 1 ps or 100 ns, 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

Anonymous
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Thanks dr JS! Thanks for helping me to better understand the situation. I updated my diagram to show the basic situation. But, naturally, the situation is likely more involved (with other factors and variables involved), but at least it's getting towards understanding how transmission lines needed for completing the delay locked loop system are taken into account. Thanks once again!

delay_locked_loop2.jpg
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