UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Newbie kakumaku23
Newbie
8,225 Views
Registered: ‎05-01-2012

ERROR:Xst:528

I am having trouble synthesizing my verilog code for a finite state machine, so I can program it onto a Basys-2 board. 

Here is the verilog code:

 

module hwten(clock, clear, w, z);
input clock, clear, w;
output z;
reg [1:0] p, Y;
parameter [1:0] A = 2'b00, B = 2'b01, C = 2'b10;

always @(w,p)
case(p)
A: if (w) Y = B;
else Y = A;
B: if (w) Y = C;
else Y = A;
C: if (w) Y = C;
else Y = A;
default: Y = 2'bxx;
endcase

always @(negedge clear)
if (clear == 0) p = A;

always @(posedge clock)
p = Y;

assign z = (p==C);
endmodule

 

And here is the error that I'm getting:

 

ERROR:Xst:528 - Multi-source in Unit <hwten> on signal <z>; this signal is connected to multiple drivers.
Drivers are:
Output signal of FD instance <p_2>
Signal <p<2>> in Unit <hwten> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <hwten> on signal <p<1>>; this signal is connected to multiple drivers.
Drivers are:
Output signal of FD instance <p_1>
Signal <p<1>> in Unit <hwten> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <hwten> on signal <p<0>>; this signal is connected to multiple drivers.
Drivers are:
Output signal of FD instance <p_0>
Signal <p<0>> in Unit <hwten> is assigned to VCC

 

Thanks for any advice

0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
8,222 Views
Registered: ‎01-03-2008

Re: ERROR:Xst:528

You are assigning a value to the "p" in two different processes and this creates two drivers connected the same net which is not allowed.

 

You are attempting to create a register with and asynchronous load (not a reset) function.  Depending on the FPGA family that you are using it maybe possible to create an asynchronous load using preset and reset pins, but the code would be a bit complicated.  It is unlikely that your design really needs this functionality and instead using should be doing this synchronously

 

always @ (posedge clock)

begin

   if (clear == 0)

      p = A;

   else

      p = Y;

end

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com