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wuchy143
Observer
Observer
6,857 Views
Registered: ‎05-25-2010

FPGA Schematic Entry

Hi All,

 

I was wondering what the common tool that is used for FPGA schematic entry? I"m using pads 2007 and it doesn't have many bga's? 

 

-mike

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8 Replies
gszakacs
Instructor
Instructor
6,848 Views
Registered: ‎08-14-2007

I'm using a very old version of ViewDraw for schematics and PADS layout for placement.  But I

always make my own symbols.  Over the years I've come not to trust anyone to do that for me.

If you want a schematic editor with more pre-built symbols, then Orcad probably is the most

popular.

 

By the way I also don't use vendor-provided decals or symbols for layout.  They rarely take

into account all of the layers and other settings used in the multilayer designs.

 

regards,

Gabor

-- Gabor
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wuchy143
Observer
Observer
6,823 Views
Registered: ‎05-25-2010

exactly what I was looking for. Thanks. 

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wuchy143
Observer
Observer
6,819 Views
Registered: ‎05-25-2010

also. 

 

I'm using a XC3S700A which has a 484 BGA. The datasheet doesn't use pin numbers. Instead they use D18, E17..etc. When I take my netlist into layout will this cause problems? Basically how does the layout tool know physically where each pin (D18, E17, etc) is physically on the PCB? 

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bassman59
Historian
Historian
6,814 Views
Registered: ‎02-25-2008

 


@wuchy143 wrote:

also. 

 

I'm using a XC3S700A which has a 484 BGA. The datasheet doesn't use pin numbers. Instead they use D18, E17..etc. When I take my netlist into layout will this cause problems? Basically how does the layout tool know physically where each pin (D18, E17, etc) is physically on the PCB? 


All reasonable modern PCB layout tools have no problems with alphanumeric pin numbers. If your chosen tool DOES have a problem, pester the vendor for an update or replace it!

 

----------------------------Yes, I do this for a living.
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mcgett
Xilinx Employee
Xilinx Employee
6,792 Views
Registered: ‎01-03-2008

All Ball Grid Array devices use a letter (A-Z) for the row and a number for the column to indentify each ball location.

 

The PCB decal defines the mapping of each ball name to the physical XY location.  This is the same methodology used for any package type.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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wuchy143
Observer
Observer
6,736 Views
Registered: ‎05-25-2010

Thanks all

 

In looking at dev board schematics and talking to other FPGA board designers it appears that FPGA's are entered into the schematic using roughly 5 different blocks. Each block consisting of: Core voltage pins, i/o voltages, aux voltage....) Is this the standard way of doing the design? If so what are each of the common blocks that fpga's break down into??

 

-mike

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gszakacs
Instructor
Instructor
6,727 Views
Registered: ‎08-14-2007

When I make FPGA symbols the number of blocks depends on the pin count of the device.

I try to make as few blocks as possible while fitting my schematic page format.  When breaking

up the device I usually use banks as the minimum unseparable portion of the FPGA and

make sure that the bank Vcco is on the same symbol as the bank I/O's to make it clearer

how the bank is powered.  I have noticed that others tend to place all powers and grounds

on a separate block that is then placed on the power supply / decoupling schematic

page.  On larger devices I also have a block for the configuration and other logic that

doesn't fit within any bank, including the Vccaux power supply pins.  Normally I use

the top and bottom of each block symbol for Vccint and ground connections respectively.

Obviously a lot of this is a matter of preference, and whatever makes sense to you

from a readability point is the best way to do it.

-- Gabor
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digisolve
Visitor
Visitor
812 Views
Registered: ‎10-25-2017

Do you have a intall disk for ViewDraw? I have sone very old FPGA designs which were done in ViewDraw 7.2, but My client no long has the install CD
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