cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
zubinkumar
Observer
Observer
17,539 Views
Registered: ‎11-23-2010

FPGA design switching between 2 clock frequencies ...

Jump to solution

hi,

 

i am working with a system where my hdl code (running on a Virtex5 board) is interfaced with an input_line (which is an input from the GPIOs). When input_line is 0, the HDL code should run at 25MHz. when the input_line is 1, the code should run at 50MHz.

 

I wanted to know what considerations I need to keep in mind when I change the clock frequency of the design as stated above. What issues could I run into? And the resolutions (if possible) ...

 

As of now, I have 2 dcms, which take a 100MHz clock input (from the Xtal on the board) and dcm1 divides the input by 4 to give 25MHz (signal name - dcm25) and dcm2 divides the input by 2 to give 50 MHz (signal name - dcm50). Then as per the value on the input_line, the corresponding frequency is sent to the rest of the desing ... like so - 

 

HDL_CLK <= dcm25 when input_line = '0' else dcm50;

 

With the above, I see some glitches in the output, even when I dont change the frequency.

 

However, when I use just 1 clock - HDL_CLK <= dcm25 .. the design works fine with no glitches in the data. So shouldn't the desing react the same way as it did, with the clock directly routed, when input_line = '0'? Why do I get a different behaviour with the "when else condition" ?

 

Also is there a more elegant, glitch free way of switching the frequencies?

 

Thanks ...

Z.

0 Kudos
Reply
1 Solution

Accepted Solutions
zubinkumar
Observer
Observer
24,968 Views
Registered: ‎11-23-2010

Thanks all ...

 

The code that finally worked for frequency switching was - 

 

FSM to select the state which would then count the source clock and divide it to give 25MHz or 50MHz.

 

And then using a BUFG to increase the fan out of the signal as I was feeding multiple sub modules ...

 

Thanks!

Z

View solution in original post

0 Kudos
Reply
6 Replies
eteam00
Instructor
Instructor
17,538 Views
Registered: ‎07-21-2009

Don't overlook the option of using a clock enable to control the clocking rate of a logic system.  For example:

  • System clock frequency is 50MHz.
  • Clock enable pulse is simply 50MHz (system clock) divided by 2 (a 1-bit counter).
  • Keep the clock enable always asserted (keep the 1-bit counter SET) for 50MHz operation.

 

Another option:

  • Generate a 100MHz clock (which you already have) to clock a small state machine (little more than a 2-bit counter).
  • Use the input control line to the state machine to generate either 25MHz (divide by 4) or 50MHz (divide by 2) output.
  • Buffer and distribute the state machine output as a global clock (either 25MHz or 50MHz).

Either of these two solutions is quite simple to implement, and is glitch-free.

Does this make sense?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Reply
avrumw
Guide
Guide
17,529 Views
Registered: ‎01-23-2009

First, you don't need two DCMs. Each DCM automatically generates CLK0/90/180/270 as well as CLK2X - if you program CLK0 for 25MHz, CLK2X is already 50MHz.

 

Second, don't use a "regular" MUX to switch frequencies (which is what your RTL MUX is doing) - they can cause glitches and and all kind of nasty stuff.

 

I presume you are going to drive this clock onto a global clock network. If so, instead of using a simple BUFG as the buffer for the global clock, use the BUFGMUX.

 

Next, be very careful with the input_line - if it is from a switch or other potentially noisy source, then you need to (heavily) debounce it before using it a clock MUX selector (unless it is only switched while the system is off or in reset).

 

Now you have to decide between a BUFGMUX or a (inaccurately named) BUFGMUX_VIRTEX4 (yes, its still called that in the Virtex5). The selector on the BUFGMUX must be synchronous to the clock output of the BUFGMUX. So, for example, if you build your debounce circuit on the output of the BUFGMUX (which should be fine), then you can use the BUFGMUX. If you use the input_line directly (as an asynchronous signal - assuming it is guaranteed not to bounce), then use a BUFGMUX_VIRTEX4.

 

The BUFGMUX/BUFGMUX_VIRTEX4 assures that the clock switching is done glitchlessly. I would suggest reading about it in the Virtex-5 User Guide.

 

Avrum

zubinkumar
Observer
Observer
17,528 Views
Registered: ‎11-23-2010

thanks bob,

 

i was actually thinking on the lines of the state machine solution you mentioned ... i will be trying that out tomm. but what i couldn't  get my head around was why, even when input_line = 0 and the HDL clock is 25MHz, with the "when else" condition, I get glitches in the o/p data. But when I directly route the 25MHz clock to the HDL clock, there are no glitches ... 

 

Any thoughts on that ?

 

Thanks and regards.

Z.

 

 

0 Kudos
Reply
avrumw
Guide
Guide
17,527 Views
Registered: ‎01-23-2009

Also, a quick follow-up to Bob's first suggestion:

  • System clock frequency is 50MHz.
  • Clock enable pulse is simply 50MHz (system clock) divided by 2 (a 1-bit counter).
  • Keep the clock enable always asserted (keep the 1-bit counter SET) for 50MHz operation

If this multiplexed clock drives a lot of logic, then you can use a BUFGCE for generating the clock, instead of routing the CE to every FF that needs it (and modifying your RTL everywhere there is a clocked process).

 

I have posted a couple of Forum answers regarding using the BUFGCE. Basically, you would take the 50MHz output of the single DCM and feed it to the I input of both a BUFG and a BUFGCE. The BUFG would generate the chip enable Bob referred to - asserted all the time if in 50MHz mode, asserted every 2nd clock if in 25MHz mode. This CE would then be connected to the CE input of the BUFGCE. The output of theBUFGCE (which is a global clock) can then clock all your logic. This uses an extra global clock buffer, but doesn't require that you modify your RTL code except for the clock generation mechanism itself.

 

Avrum

eteam00
Instructor
Instructor
17,523 Views
Registered: ‎07-21-2009

but what i couldn't  get my head around was why, even when input_line = 0 and the HDL clock is 25MHz, with the "when else" condition, I get glitches in the o/p data. But when I directly route the 25MHz clock to the HDL clock, there are no glitches ...

 

You need to understand that combinatorial logic built from LUTs (most of the logic in Xilinx FPGAs) will glitch when inputs change -- and a LUT with a 25MHz clock and a 50MHz clock input definitely has changing inputs!

 

In case you weren't aware, a LUT is a small memory or RAM, and the logic inputs are essentially RAM address inputs.

 

On the other hand, register outputs are glitch-free, and clocks generated directly from register outputs will also be glitch-free.

 

Bottom line:

  • LUT output used as a clock?  NO!
  • Register output used as a clock?  OK!

Does this make sense?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Reply
zubinkumar
Observer
Observer
24,969 Views
Registered: ‎11-23-2010

Thanks all ...

 

The code that finally worked for frequency switching was - 

 

FSM to select the state which would then count the source clock and divide it to give 25MHz or 50MHz.

 

And then using a BUFG to increase the fan out of the signal as I was feeding multiple sub modules ...

 

Thanks!

Z

View solution in original post

0 Kudos
Reply