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Participant teraser
Participant
7,396 Views
Registered: ‎11-18-2010

Firmware for faster speedgrade

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Hello!

 

If i've got working design for, say, Virtex5 -1 speedgrade, will the same binary file work correct in the same Virtex5, but -2 or -3 speedgrade?

 

Regards.

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Teacher eteam00
Teacher
12,332 Views
Registered: ‎07-21-2009

Re: Firmware for faster speedgrade

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If you are asking if synchronous designs work reliably on all speed grades of Virtex-5 devices - - up to a datasheet frequency limit --  the answer is yes, of course they do

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Teacher eteam00
Teacher
7,389 Views
Registered: ‎07-21-2009

Re: Firmware for faster speedgrade

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The answer is, generally, YES.

 

Keep in mind that a -1 speed grade device may be faster than a -2 or -3 speed grade device.  The speed grade under which a Xilinx FPGA is sold means that the device has been tested to meet certain MINIMUM levels of performance.  The extent to which the device EXCEEDS this minimum level of performance is not tested or guaranteed, unless it is explicitly declared in the device datasheet (i.e. maximum propagation delay is often specified, but not minimum propagation delay).

 

This is one of the reasons that asynchronous design is a dodgy practice which is not supported by Xilinx.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Instructor
Instructor
7,388 Views
Registered: ‎08-14-2007

Re: Firmware for faster speedgrade

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Yes.

 

The minimum delay times used for all speed grades are based on the fastest speed grade.  So you won't suddenly end up with hold time errors with a faster speed grade part.  In addition, you should be aware that a part marked -1 could actually meet -2 or -3 speed, but was not tested to that speed grade.  As products mature, the percentage of product that meets the faster speed grade requirements goes up until at some point Xilinx needs to ship some faster product to meet demand for slower speed grade orders.

-- Gabor
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Participant teraser
Participant
7,356 Views
Registered: ‎11-18-2010

Re: Firmware for faster speedgrade

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Bob,

That "generally" bothers my mind :)

 

When I look into a timing report for two PVT corners, I see "fastest" and "slowest" delays for data and clock lines analyzed. I'm using synchronous design, without any hint of "undocumented tecniques", but:

Can I be absolutely sure, that if I've got tight design, that has ones of picoseconds margin in one of PVT corners - that margin will not be violated in another speedgrade device?

Can I be absolutely sure, that if "data" will come 10 ps earlier in another speedgrade - "clock" won't come another 10 ps earlier than "data"? :)

 

Thank you.

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Teacher eteam00
Teacher
12,333 Views
Registered: ‎07-21-2009

Re: Firmware for faster speedgrade

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If you are asking if synchronous designs work reliably on all speed grades of Virtex-5 devices - - up to a datasheet frequency limit --  the answer is yes, of course they do

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Participant teraser
Participant
7,322 Views
Registered: ‎11-18-2010

Re: Firmware for faster speedgrade

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Thank you both, Bob and Gabor.

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Dies diem docet.
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