I have a vhdl module i would like to instanciate several times.
In order to be able able to easaly change the number of module i would like this instanciation to be generic...
for i in 0 to Nb_elements generate
uut : CLK_def PORT MAP (
Clk => Clk,
Raz => Raz,
Sig_A => Sig_A(i),
Sig_B => Sig_B(i)
Thank you for your help,
That'll work; simply put Nb_elements in your entity's generic list.
Make sure that you use that generic to set the width of the Sig_A() and Sig_B() vectors.