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guilvard
Adventurer
Adventurer
2,492 Views
Registered: ‎03-05-2009

Generic instanciation of a module ?

Hello,

 

I have a vhdl module i would like to instanciate several times.

In order to be able able to easaly change the number of module i would like this instanciation to be generic...

 

for i in 0 to Nb_elements generate uut : CLK_def PORT MAP ( Clk => Clk, Raz => Raz, Sig_A => Sig_A(i), Sig_B => Sig_B(i) ); end generate;

 

 

 

 Thank you for your help,

 

Alex

 

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bassman59
Historian
Historian
2,484 Views
Registered: ‎02-25-2008

That'll work; simply put Nb_elements in your entity's generic list.

 

Make sure that you use that generic to set the width of the Sig_A()  and Sig_B() vectors.

----------------------------Yes, I do this for a living.
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