cancel
Showing results for
Show  only  | Search instead for
Did you mean:
Newbie
5,976 Views
Registered: ‎04-24-2010

## Help for GAL(urgent)

If the sequence chart is like this, what the code should be ?
Thanks

Message Edited by mpy on 04-24-2010 03:45 AM
Tags (1)
7 Replies
Teacher
5,959 Views
Registered: ‎07-09-2009

HI

I htink a GAL was an old PLD, 25 odd years ago ?

was it Xilinx ?

Anyway, fomr the diagram,

it's impossible to say.

Which are inputs which outputs ?

Is it a clocked sequance ?

As a general thought, assuming two are inputs and one is output, write a Karnough map / table for the 4 cases,

see what you get is a good start.

I'm guessing you have some sort of SR latch circuit,

output goes high when M goes high, output goes low when H7 goes low,

but what happens in the other cases ( i.e. M high and H7 low ) is a good quesion ?

Professor
5,949 Views
Registered: ‎08-14-2007

GALs were made by Lattice, and he posted the same question on their

-- Gabor
Teacher
5,947 Views
Registered: ‎07-09-2009

Hi gs,

yep sort of guessed he was fishing, hence comments to get him to think a little bit

I guess were here to 'pass on' our knowledge to the young ones, sort of modern day apprenticeship !

Teacher
5,926 Views
Registered: ‎08-14-2007

Hi John,

you guessed right about the inputs and outputs. (The waves are marked with I and O  at the beginning. :-)  )

It is a set-reset behavior, but a strange one, since the output changes on the falling edge of the setting signal and on the rising edge of the resetting signal.

Even if it's a clocked process, how should the output know, when the resetting input will be activated?

Unfortunately the timeline is not very helpful, because it's not properly fitting the quantisation of the signals. (A clock would be really helpful.)

If you take a closer look, you see that the setting input (M) has different impulse legth, and so does the output.

My guess is that we are looking at a pulse stretching circuit:

t(db10) = k*t(M)

According to the dashed fields, I suspect that the other input is not really involved, but just an external reaction (like some kind of handshake) from some connected circuit.

But all of this is kind of speculative, since the purpose of this circuit is unknown.

Have a nice synthesis

Eilert

Teacher
5,925 Views
Registered: ‎07-09-2009

HI Eilert,

I try hard not to read too much into names,

ever since working with a company that had names like 'data_out',

but then that was an input to the receiver !

Isn't it fun trying to guess what the circuit doesfrom so little information.

It would be even more fun if the poor guy had to impliment this,

As you say, are the pulse widths important ? what happens in the cases that are not shown !

Ah well,

Professor
5,922 Views
Registered: ‎08-14-2007

That's a good point.  The M input looks like it needs to use its falling edge to

set the output, but given the information you don't know whether the H7 input

is also a falling edge triggered reset or an asynchronous active low reset.   I

usually have to wonder if this sort of thing is an academic exercise (from the

"urgent" in the title - translate to "due soon"), or some sort of reverse Engineering,

common with parts of this vintage.

Regards,

Gabor

-- Gabor
Xilinx Employee
5,771 Views
Registered: ‎09-07-2009

Use a D FF and async reset can do this

always @(negedge H7 or negedge M)

if(!M)  DB10 <= 1;

else if(!H7) DB10<=0;