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Anonymous
Not applicable
7,803 Views

How to auto reset or auto initialize the counter

Hi,
             I am sending data format serially on every rising edge clock.  Assume i am sending 4 packets of 12 bit information.
 In that 1 packet bit information is like this.
 1st bit                   - start bit    
 2nd bit to 9th bit  - Pixel data bits
 10th bit                 - Line Valid bit
 11th bit                 - Frame Valid bit
 12th bit                - stop bit.
                     these bits data is coming from test bench serially.I should convert this to parallel data.So i implimented 5 counter to convert serial data to parallel data.
cnt4        for start bit(1st bit).
cnt5        for Pixel data bits (2nd to 9th bit)
cnt6        for Line valid bit
cnt7        for Frame valid bit
cnt8        for Stop bit.
                    all the counter is implimented in if statement. Countinuously i am concating bits if "if statement" is not satisfied.Suppose "if statement" satisfied data is picked from variable. After cnt4 satisfies it goes for cnt5 and continue upto cnt8.After again am intialising these 5 counters. So for initializing process i need 1 clock cycles.So 1 bit data i am missing after 1 packet.How to avoid this ?

                    I attached the waveforms here.For stop bits converting it is taking two pixel clocks or i can say after stop bit i need 1 clock cycle for initializing counter.So i am loosing second packet first information i mean some junk value is picking on read_data_s varible.

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12 Replies
joelby
Advisor
Advisor
7,793 Views
Registered: ‎10-05-2010

What you are trying to achieve is very unclear from your description. Are you trying to create a 12-bit deserialiser? This should be trivial to do with a simple state machine and a single counter. Can you post the code you have at the moment?

 

 

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eteam00
Instructor
Instructor
7,791 Views
Registered: ‎07-21-2009

After again am intialising these 5 counters. So for initializing process i need 1 clock cycles.So 1 bit data i am missing after 1 packet.How to avoid this ?

 

It appears there is a state after cnt8 in which the counters are initialised.  Correct?

 

If yes, then the simple correction is to use cnt8 state to initialise the counters, and eliminate the extra counter initialisation state from your state machine.

 

Perhaps I am misunderstanding your description.

 

So i implimented 5 counter

 

You implemented 5 different counters?  Or a 5-bit counter?  Or a state machine with 5 states?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

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4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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Anonymous
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Hi,

        I didn't used state machine here.I used 5 counters not a 5 bit counter.

I am sending this data from my test bench.

Line Valid       -- LV

Frame Valid   -- FV

Info about the data ---header1, FV Assertion ,Header2, LV Assertion, start bit,8 bit data, LV,FV,Stop bit,LV deassertion           , FV Deassertion

Data Sent from TB ---1023      ,              0         ,     1023  ,           1          ,       1      ,       55      ,   0 , 1 ,     1       ,   2                  ,               3  ..

this is wt i am sending the serial data from my test bench.

So i am using 9 counters to deserialize the above data.

cnt                       used  to get header1(1023).

cnt1                     used  to get FV assertion(0).

cnt2                     used  to get header2 (1023).

cnt3                     used to get LV assertion (1).

cnt4                     used to get Start bit (1).

cnt5                     used to get 8 bit data

cnt6                     used to get LV.

cnt7                     used to get FV.

cnt8                     used to get stop bit.

cnt9                     used to get LV deassertion.

cnt10                   used to get FV deassertion.

 

                                I will get sensor data as a input.Sensor has no of rows into no of columns of pixels.In read out process sensor will give serial data on each rising edge of pixclk.Supose sensor is having 752 columns and 480 rows.So 1 pixel data is nothing but 1 packet. In 1 packet

Start bit        -- 1 bit.

Pixel data    -- 8 bits.

LV                 -- 1 bit.

FV                 -- 1 bit.

Stop bit        -- 1 bit.

                                Continuously i will get the packets.So i should initialize cnt4,cnt5,cnt6,cnt7,cnt8 after deserializing first packet.After stop bit i need 1 pixclk to reinitialise these counters.So i miss the start bit of next packet.How to avoid this?

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eteam00
Instructor
Instructor
7,779 Views
Registered: ‎07-21-2009

I didn't used state machine here.I used 5 counters not a 5 bit counter.

 

Maybe it's time to consider using a state machine.  Do you have experience with state machine design?  Is there a particular reason you do NOT want to use a state machine?

 

After stop bit i need 1 pixclk to reinitialise these counters.So i miss the start bit of next packet.How to avoid this?

 

The answer is completely obvious, if you want to stick with your existing design.  The answer is to initialise your counters early enough so that you do not miss the start bit of the next packet.  This is nothing more or less than a minor bug in your design which you need to correct.

 

I can't tell you anything more than this, because your description is completely vague and absent useful details.  We cannot see what is in your head and which you do not write in your posts.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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joelby
Advisor
Advisor
7,778 Views
Registered: ‎10-05-2010

Without seeing your code it's still hard to know what you can do to fix this, but this operation seems like a perfect candidate for a state machine. Is there any reason why you're not using one?

 

  • Is there any dead time between successive packets?
  • Is pixclk clocked during the inter-packet space, or does it only run while data is being sent?
  • Are you clocking the FPGA using pixclk?
  • How fast is pixclk, and how fast are your system clock(s)?

 

 

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Anonymous
Not applicable
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Hi,

            I  added the FSM here.By this FSM i am  not able to get the header properly in read_data_s variable.In read_data_s i should get as 1023,0,1023,1 like this i should get.Valid data am getting in read_data_s.But in read_data some junk value i am getting.

---------------------------------------------------------------------------------------------------------------------------------------------

process(pix_clk)
begin
if(falling_edge(pix_clk)) then
    if(resetn_i = '0') then
    control_state    <= HEADER1_ST;
    elsif(resetn_i = '1') then
case control_state is
when HEADER1_ST =>
    if(cnt = 16) then
        read_data_s    <= read_data;
        control_state    <= FV_ASSERT_ST;
    else
        cnt        <= cnt + 1;
        read_data    <= read_data(14 downto 0) & serial_data;
        control_state    <= HEADER1_ST;
    end if;
when FV_ASSERT_ST =>
    if(cnt1 = 1) then
        read_data_s    <= read_data;
        control_state    <= HEADER2_ST;
    else
        cnt1        <= cnt1 + 1;
           read_data    <= "000000000000000" & serial_data;  
           control_state    <= FV_ASSERT_ST;
    end if;
   
when HEADER2_ST =>
    if(cnt2 = 16) then
        read_data_s    <= read_data;
        control_state    <= LV_ASSERT_ST;
    else
        cnt2        <= cnt2 + 1;
             read_data    <= read_data(14 downto 0) & serial_data;
             control_state    <= HEADER2_ST;
       
    end if;

when LV_ASSERT_ST =>
    if(cnt3 = 1) then
        read_data_s    <= read_data;
        control_state    <= PACKET_START_ST;
    else
        cnt3        <= cnt3 + 1;
             read_data    <= "000000000000000" & serial_data;
             control_state    <= LV_ASSERT_ST;
    end if;

when PACKET_START_ST =>
    if(cnt4    = 1) then
        read_data_s    <= read_data;
        control_state    <= PIXEL_DATA_ST;
       
    else
        cnt4        <= cnt4 + 1;
             read_data(0)    <= serial_data;
             control_state    <= PACKET_START_ST;
    end if;
   
   
when PIXEL_DATA_ST =>
    if(cnt5 = 8) then
        read_data_s    <= read_data;
        control_state    <= LV_PACKET_ST;
    else
        cnt5        <= cnt5 + 1;
             read_data    <= "0000000" & read_data(7 downto 0) & serial_data;
             control_state    <= PIXEL_DATA_ST;
     
    end if;

when LV_PACKET_ST =>
    if(cnt6 = 1) then
        read_data_s    <= read_data;
        control_state    <= FV_PACKET_ST;
    else
        cnt6        <= cnt6 + 1;
        read_data    <= "000000000000000" & serial_data;
        control_state    <= LV_PACKET_ST;
       
    end if;

when FV_PACKET_ST =>
    if(cnt7    = 1) then
        read_data_s    <= read_data;
        control_state    <= PACKET_STOP_ST;
    else
        cnt7        <= cnt7 + 1;
        read_data    <= "000000000000000" & serial_data;
        control_state    <= FV_PACKET_ST;
       
    end if;
   
when PACKET_STOP_ST =>
    if(cnt8 = 1) then
        read_data_s    <= read_data;
        control_state    <= PACKET_START_ST;
    else
        cnt8        <= cnt8 + 1;
             read_data    <= "000000000000000" & serial_data;
             control_state    <= PACKET_STOP_ST;
            
    end if;
   
when others => null;

end case;
    end if;
end if;
end process;
   
   
parallel_data    <= read_data_s;

image.JPG
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joelby
Advisor
Advisor
7,773 Views
Registered: ‎10-05-2010

This looks far more complicated than it needs to be.

 

  • Define one packet data register, wide enough for an entire packet.
  • In idle state, wait for start bit
  • Shift bit in to the packet data register
  • Count bits OR continue until you detect a stop bit (depending on the nature of the packet)
  • When finished, copy packet data register to another register, or a bunch of registers if you want to keep the different fields separate.
  • Reset bit counter, return to idle state

With the current approach I'm not quite sure how you're signalling to some other process that read_data has become valid at the end of some state, and the data will only be valid for a single cycle before something else overwrites read_data. With my approach, you'd decode the whole packet in one go, signal that data is ready at the end, and then have plenty of time to deal with it.

 

If you're getting junk and want to debug your current approach, you should simulate it. Without your test bench and complete module it is impossible for us to replicate your results, and even with it, it's difficult to figure out what your intent is.

 

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joelby
Advisor
Advisor
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Registered: ‎10-05-2010

Now that you've added the simulation output.. what do you mean by "in read_data_s i should get as 1023,0,1023,1"? I presume that read_data_s is a 16-bit register, so it can only have one value at a time.

If you mean that it should take the values 1023, 0, 1023, and 1 over four consecutive clock cycles, then I can't see how this could happen if you're deserialising an input and shifting it in from the least significant bit.
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Anonymous
Not applicable
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Hi,

         read_data_s is a 16 bit register.1023 is the hex value.0 & 1 are the bits.So i am taking all the values into 16 bit register.

if i convert 1023 into binary  i will get "0001000000100011".I am sending this data from my test bench.So i need 16 clock cycles for this.for 0 1 clock cycle is required.agian for 1023 16 clock cycle is required.After this for deserialising '1' i need 1 clock cycle.I am deserilising this values.

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Anonymous
Not applicable
3,236 Views

Hi,

@eteam00 In the begining before posting i didn't thought about FSM.i used FSM and added the code also.Here i am not getting correct headers itself.

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joelby
Advisor
Advisor
3,235 Views
Registered: ‎10-05-2010

Why not just deserialise in to one long register and not worry about what's in it until the end?

You should be able to see exactly what is happening in the simulation by examining the state variable, the counters, the input data and the read_data_s register.
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Anonymous
Not applicable
3,233 Views

Hi,

   See the data format in figure.p41 is 12 bit packet. In that 12 bit

1st bit-start bit

2nd to 9th bit - 8 bit pixel data.

10th bit - 1 bit LV info

11th bit - 1 bit FV info

12 th bit - Stop bit.

p41 to p46 -  first frame data,

p51 to p56 - second frame data.I shoud get like this finally in read data_s.
0- Frame Valid Assertion Indication
1- Line Valid Assertion Indication
2- Line Valid deassertion
3- Frame Valid Deassertion

Data_format.JPG
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