02-08-2021 02:29 AM
I need to build a communication system between two FPGA (ZYNQ 7020). I use oserdese2 and iserdese2. I implemented the bit slip operation to align the data in iserdese2. When increasing the frequency, I need to implement the bit align to put the clock in the middle of the data. I need to use iodelay2 in a variable mode that adjusts the delay between the clock and the data. I read a lot of application notes and threads on the forum. In my case, I don't have a frame signal. I have to do training to do bit align. The application notes 855 ìs seem ok for my scope. In section Dynamic Timing and BIT_ALIGN_MACHINE, the sentences "But what if the jitter is extremely deterministic? The transition then has discreet crossing points,
such that within the transition there is very stable, but incorrect, data. In this case, the algorithm
does not sense any instability and falsely concludes that the sampling point is not in the
transition. To address this case, apart from evaluating stability, the algorithm also evaluates the
correctness of the data content by using the bitslip feature in the middle of the transition. For
example, if the algorithm determines that the sampled data is stable, it then asserts bitslip to
look for the correct data. If 0x2c is found within eight assertions of bitslip, then the sampling
point is not in the transition. But if 0x2c is not found, then the algorithm increments the data
delay and repeats the transition test again. "
generates a lot of confusion. Why the deterministic jitter case, when asserting the bit slip and the training word found within 8 cycles is wrong? In other words, I never the correct alignment.
Any suggestions for this question or how to build a bit align state machine are welcome.
02-08-2021 02:54 AM
Thanks for your response. I read a lot of application notes the best for me is the 855. When it's starting to explain the determinist jitter case, I don't understand the mechanism to discharge the sampling point " If 0x2c is found within eight assertions of bit slip, then the sampling point is not in the transition ". I want to do the state machine from scratch. The mechanism for bit alignment is not very clear in the case of the deterministic jitter.
02-08-2021 03:18 AM
I think your question (how to build a bit align FSM) and your actual problem (how to deal with extreme deterministic jitter) are different.
First, is your data stream going to show extreme deterministic jitter? In other words: is what you have an actual problem or a doubt?
With a mild deterministic jitter on top of random jitter, a SM could just work well. The clock might be at 45 or 55% of the data slot.
What frequencies are we talking about?
02-08-2021 03:58 AM
You have right. I do a bit confused. My first question is how to do a state machine for bit align with iodelay. The second question is how to do in the case of deterministic jitter. The frequency starts to 100MHz up to 400/500 MHz
02-08-2021 04:34 AM
My suggestion: don't over-complicate things. Real life is already extremely generous in that. Try a basic design. If it works, that's it, hats off! If it doesn't, let's think about it. "step by step development", "fail quick" and all that engineering self-help sort of stuff.