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Visitor
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Registered: ‎05-16-2017

How to build an Ethernet switch?

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Hi everyone!

 

Recently I am trying to build an Ethernet Switch. The system receives frames from PHY and MAC, and then extracts frame's destination MAC address (DA), and next, looks up for the DA in lookup table to determine the output port. And my question is how to build a lookup table? I can't find any useful information in the Internet, so any suggestion is of great appreciation.

 

A simple should include how to extract Destination Address & Source Address, how to look up efficiently, and maybe more..

 

Thank you!!

switch_2x2_framework.png
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Scholar
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Registered: ‎08-07-2014

Re: How to build an Ethernet switch?

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And my question is how to build a lookup table?

 

Look-up tables above a certain size will be always implemented using block RAM.

So you may implement a lookup table by:
- generating the initialization file (e.g. *.coe) in a spread sheet calculator or math tool.
- describing the look up table completely in VHDL or Verilog

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Registered: ‎01-08-2012

Re: How to build an Ethernet switch?

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@terumi wrote:
And my question is how to build a lookup table

I'm not sure whether you mean "how do I code a lookup table in an FPGA" or "how do I know which MAC addresses to use to populate the table?

If it's the latter, I suggest reading a book (remember books?).

The Switch Book by Rich Seifert.  Wiley.  ISBN 0-471-34586-5

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Scholar
Scholar
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Registered: ‎08-07-2014

Re: How to build an Ethernet switch?

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And my question is how to build a lookup table?

 

Look-up tables above a certain size will be always implemented using block RAM.

So you may implement a lookup table by:
- generating the initialization file (e.g. *.coe) in a spread sheet calculator or math tool.
- describing the look up table completely in VHDL or Verilog

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------

View solution in original post

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Visitor
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Registered: ‎05-16-2017

Re: How to build an Ethernet switch?

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Thank you so much for your suggestion! And I will read the book.

 

While my question is how to code a lookup table in Verilog.  Since there is little information about how to build a table and how to search in the table. So I wonder if there are some open source codes about it(or about Ethernet Switch), so that I can learn from.

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Registered: ‎05-16-2017

Re: How to build an Ethernet switch?

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Yeah, this answer is what I want! Thank you!

 

And I wonder if your method only fits to build a static lookup table? How to build a dynamic lookup table? Is the method similar? Cause there is learning and aging operation in an Ethernet Switch, so the lookup table is supposed to be able to delete or rewrite items dynamically.

 

Are there any reference materials or open source codes?

 

Again, thanks a lot!

 

 

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Registered: ‎01-08-2012

Re: How to build an Ethernet switch?

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I think you should purchase / borrow and read the book before worrying about how to code up the lookup mechanism in the FPGA.

 

Firstly, the switch will have a "data plane" and a "control plane".  The data plane is implemented in your FPGA fabric and is responsible for high speed forwarding of packets, based on tables set up by the control plane.  The control plane is typically implemented in software (e.g. on a CPU) and deals with higher level protocols, network topology learning, etc. and will configure the tables in the data plane.

The data plane is responsible for recognising packets that it doesn't understand and sending them "up" to the control plane for analysis.

 

The tables that you are asking about (for your homework assignment?) are all in the data plane.

 

For a switch, you may need to apply rules based on MAC addresses.  First separate out the broadcast and multicast addresses.  The remaining 47 bits of MAC address are an input to your table.  But 2**47 is a huge number, greatly exceeding the size of any RAM you can attach to an FPGA.  This suggests a different type of lookup table, perhaps a hash table or other data structure suited to sparse lookups.  A quick web search reveals that a SOHO switch might have storage for a few thousand MAC addresses.

 

For a switch, you may also need to apply rules based on VLAN tags.  These are only 12 bits long, so you can use the obvious table implementation.

 

For a router (as opposed to a switch) you may need to apply rules based on MPLS labels.  These are 20 bits long, so you may or may not be able to use the obvious table implementation.

 

Regards,

Allan

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