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Voyager
Voyager
1,110 Views
Registered: ‎10-12-2016

How to compare timing reports as FPGA and ASIC technologies are different ?

Hi Friends,

 

ASIC and FPGA implemented technologies are different , then how we have to make sure proper timing analysis ?

 

NOTE: Any help or suggestions are highly appreciated ?

 

Thank You

S Sampath

-Sampath
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Explorer
Explorer
1,022 Views
Registered: ‎05-08-2018

s,

 

Are you prototyping an ASIC in a FPGA device?

 

If so, down load and read "FPGA Prototyping Methodology Manual" (Xilinx & Synopsys):

 

https://www.synopsys.com/company/resources/synopsys-press/fpga-based-prototyping-methodology-manual.html

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Observer
Observer
608 Views
Registered: ‎05-14-2018

The tool of fpga either quartus and vivado takes care of timing analysis. If required clock is need to be specified it is given in the constraints file.
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