08-18-2018 08:37 PM
ASIC and FPGA implemented technologies are different , then how we have to make sure proper timing analysis ?
NOTE: Any help or suggestions are highly appreciated ?
08-19-2018 07:07 AM
Are you prototyping an ASIC in a FPGA device?
If so, down load and read "FPGA Prototyping Methodology Manual" (Xilinx & Synopsys):
10-06-2018 06:46 AM