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Visitor mitchherkert
Visitor
2,691 Views
Registered: ‎03-11-2014

How to implement an inverter bubble in ISE?

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Is there a way to use just a bubble inverter in ISE? Currently I am using buffers with an inverter on my inputs, but I would rather just put a bubble on the gates in order to have 4 inputs instead of 8. Thanks.

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Xilinx Employee
Xilinx Employee
3,236 Views
Registered: ‎08-02-2007

Re: How to implement an inverter bubble in ISE?

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Hi,

 

You can use them in schematics.

 

Refer to page 54 of http://www.xilinx.com/itp/xilinx10/books/docs/virtex5_scm/virtex5_scm.pdf

 

--Hem

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Xilinx Employee
Xilinx Employee
3,237 Views
Registered: ‎08-02-2007

Re: How to implement an inverter bubble in ISE?

Jump to solution

Hi,

 

You can use them in schematics.

 

Refer to page 54 of http://www.xilinx.com/itp/xilinx10/books/docs/virtex5_scm/virtex5_scm.pdf

 

--Hem

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Give Kudos to a post which you think is helpful and reply oriented.
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