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Explorer
Explorer
10,145 Views
Registered: ‎03-10-2015

ILA display issue?

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Hello,

 

  Can someone to tell me why the second cycle is longer? 

 

Regards, Fred

ILA_CLK_data_issue.PNG
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Historian
Historian
18,737 Views
Registered: ‎01-23-2009

Re: ILA display issue?

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1) The data is generated on rising edge but the reciever is sampling on falling edge and I wanted to view both the dada and reciever clock at the same time. It seems like as I can't do that?

 

Are the source and destination both inside the FPGA? If so, why would you sample on the negative edge of clocks - that's not normal synchronous design...

 

But the answer is no - you would have to do something like what you are doing - oversampling on a faster clock.

 

2) By the way what is the unit (ms, us, ??) showing on top of the graph?

 

That's the whole point - it is in SAMPLES. A logic analyzer is not an oscilloscope, it is not sampling on a continuous time line, it is sampling on the edges of the sampling clock (which you said was 100MHz). Thus, each sample represents the state of the data on each consecutive rising edge of the sampling clock. Since your clock is 100MHz, each sample is 10ns apart.

 

3) can I instruct the ILA to trigger on next edge that it find?

 

Yes - the ILA has lots of capability. But some of the functionality of the ILA is configured at ILA generation time; to do edge triggering, you may have needed to configure that when you generated the ILA (I am not a Vivado Logic Analyzer / Chipscope expert).

 

Avrum

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Voyager
Voyager
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Registered: ‎04-21-2014

Re: ILA display issue?

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Fred: Ever look up into the sky, and see geese flying in a V formation? Did you ever wonder why one of the legs in the V is longer than the other? Because there are more geese in the longer leg. :)


@fsahebi2014 wrote:

Hello,

 

  Can someone to tell me why the second cycle is longer? 

 

Regards, Fred


 

Short answer: Because it was sampled a static a larger number of clocks.

Otherwise, we need more context.

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***
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Historian
Historian
10,017 Views
Registered: ‎01-23-2009

Re: ILA display issue?

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You have to realize that the ILA is an "Internal Logic Analyzer", so that means that it is digitally sampling signals using a sampling clock. The "waveform" you see is actually just a plot of these sampled values on each successive sample.

 

In this capture, it looks like you are sampling a clock. So, on each rising edge of your sampling clock it is going to measure whether the sampled signal is a 1 or a 0. Lets say your sampled clock is 1/3 the frequency of your sampling clock; this means that you should (on average) get 1 1/2 samples where the sampled signal is low and 1 1/2 clocks where it is high. But it is a logic analyzer so can only give you samples on each rising edge of your sampling clock - it can't show "1 1/2" samples, it can only show 1 or 2. So you will see each of the low and high time either as being 1 sample or 2. They will average out to 1 1/2 over the a long enough period, but each one will be 1 or 2.

 

The same may be happening here; you could be trying to sample a clock that is just slightly slower than 1/2 your sampling clock - you are seeing 2 samples high (6503 and 6504), then 1 sample low (6505), 1 high (6506), 1 low (6507), 2 high (6508 and 6509), etc...

 

However, you have to be REALLY careful here, it is also possible that this "clock" you are sampling is not at all the observed frequency; for example if it were just slightly slower than 2x the clock frequency of the sampling signal, you could get a similar looking waveform - again, your ILA would sample the signal once per sampling clock; between (say) 6503 and 6504, it may have been high (at 6503), then gone low and then gone back high (at 6504) and you won't be able to tell. This would still look "periodic" based on the harmonics of the sampled and sampling clocks - this is called "aliasing".

 

To make sure you are not aliasing, you must sample a periodic signal with a sampling rate at least 2x the frequency of the signal - higher (and preferably much higher) is better. If you were to sample this at 100 times the frequency of the sampled signal, you would still see this distortion, but your low and high time would only bounce around by 1 count on 50; i.e. the low time would sometimes be 49 samples and sometimes 50 samples - this would look much more like a "clock".

 

Avrum

Explorer
Explorer
9,972 Views
Registered: ‎03-10-2015

Re: ILA display issue?

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Hi Avrum,

 

  Thanks so much for your explanation... The sampled clock is 40MHZ, and data generated using 40MHZ clock but ILA clock is set to 100MZ. 

 

In general is you want to sample both clock and data what is the reasonable CLK for ILA to display things correctly?

 

Best regards, Fred

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Historian
Historian
9,962 Views
Registered: ‎01-23-2009

Re: ILA display issue?

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In general is you want to sample both clock and data what is the reasonable CLK for ILA to display things correctly?

 

No, in general, you want to use the ILA as a logic analyzer. A logic analyzer is (primarily) intended to debug synchronous systems by capturing the state of the system during each cycle. So, if this is a simple synchronous system (the entire system is running on the same clock), then the normal way of using a logic analyzer is to sample the signals of interest using that exact same clock that the system is running on (and, consequently not "sample" the clock at all). Thus, the logic analyzer will give you the state of the system on each successive clock cycle; the sample at ILA sample 6503 will give you the state of the system on that rising edge of clock, the sample at 6504 will give you the state of the system on the next clock, and at 6505 will give you the state on the rising edge of the clock after that.

 

So if your system is running at 40MHz, use the same 40MHz clock that is clocking your state machine as the sampling clock of the ILA.

 

Clearly if you do this, you cannot sample the clock - you will not be able to see any clock signal in your ILA capture. Again, that is normal - the clock is implicit; every sample of the ILA represents the state of the system on a successive rising edge of the clock.

 

Avrum

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Explorer
Explorer
9,951 Views
Registered: ‎03-10-2015

Re: ILA display issue?

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Thanks ...

1) The data is generated on rising edge but the reciever is sampling on falling edge and I wanted to view both the dada and reciever clock at the same time. It seems like as I can't do that?

 

2) By the way what is the unit (ms, us, ??) showing on top of the graph?

 

3) can I instruct the ILA to trigger on next edge that it find?

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Historian
Historian
18,738 Views
Registered: ‎01-23-2009

Re: ILA display issue?

Jump to solution

1) The data is generated on rising edge but the reciever is sampling on falling edge and I wanted to view both the dada and reciever clock at the same time. It seems like as I can't do that?

 

Are the source and destination both inside the FPGA? If so, why would you sample on the negative edge of clocks - that's not normal synchronous design...

 

But the answer is no - you would have to do something like what you are doing - oversampling on a faster clock.

 

2) By the way what is the unit (ms, us, ??) showing on top of the graph?

 

That's the whole point - it is in SAMPLES. A logic analyzer is not an oscilloscope, it is not sampling on a continuous time line, it is sampling on the edges of the sampling clock (which you said was 100MHz). Thus, each sample represents the state of the data on each consecutive rising edge of the sampling clock. Since your clock is 100MHz, each sample is 10ns apart.

 

3) can I instruct the ILA to trigger on next edge that it find?

 

Yes - the ILA has lots of capability. But some of the functionality of the ILA is configured at ILA generation time; to do edge triggering, you may have needed to configure that when you generated the ILA (I am not a Vivado Logic Analyzer / Chipscope expert).

 

Avrum

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