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berker_atel
Adventurer
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Registered: ‎11-09-2016

Implementation timing NA problem

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Hi,

I have two constraints in my design.

I can see timing results after synthesis, but i can't see after implementation. I'm sure .xdc file used for both synthesis and implementation.

create_clock -name dec_clk -period 37.037 [get_ports dec_clk]
create_clock -name processing_system7_0_FCLK_CLK0 -period 10 [get_pins processing_system7_0/FCLK_CLK0

 

My problem is, i can't get timing results. Screenshot from 2017-10-04 22-37-36.png

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berker_atel
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Registered: ‎11-09-2016

Hi,

The logic do nothing because output of logic don't go anywhere. Vivado thinks this logic unconnected and not used, it remove unnecesarry logic in optimization.

If anyone face the same problem, can check below link:

https://forums.xilinx.com/t5/Timing-Analysis/Hold-violation/m-p/798766#M12467

 

Thanks

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u4223374
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Registered: ‎04-26-2015

The reason for the lack of timing is shown on the far right of your screenshot: 0 LUTs and 0 FFs. Vivado has optimized away your entire design, and if there's no design then there can't be timing. Have a look through the log and see why it's been optimized away.

berker_atel
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Registered: ‎11-09-2016

Thanks @u4223374

I disable opt_design in implementation settings. Vivado can place&route now.

t2.png

But, timing results are NA still.Is there one more problem?

Why Vivado optimize doing unplace/unroute? Is there a coding or design problem?

 

Best Regards

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berker_atel
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Registered: ‎11-09-2016

Also,

I attached implementation LOG results.

 

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syedz
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Registered: ‎01-16-2013

@berker_atel,

 

Definitely the coding problem. It is not recommended to disable the opt_design stage which is on by default.  From the shared log file, I see sweep stage is removing unconnected cells and nets. 

Capture.JPG

 

 

Rerun opt_design with -verbose switch to know detailed optimization report.  See the below thread to add -verbose switch in implementation setting

https://forums.xilinx.com/t5/Implementation/Which-logfile-details-optimization-results-Vivado-2017-2/m-p/798537#M18938

 

Now the log file will contain the name of the optimized cells and you can check those connections in synthesized design.

 

--Syed

 

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Did you check our new quick reference timing closure guide (UG1292)?
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yashp
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Registered: ‎01-16-2013

Hi,

 

There is definitely a design issue.

I can give you hint where to look for, always check for warning/critical warnings and errors.

If you solve each one by one you will get the best answer.

 

If after proper design, if you still face timing analysis is not performed by tool on implemented design.

See is there any message associated with it.

 

But for now this looks more specific to design than timing/tool issue.

 

Thanks,
Yash

 

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berker_atel
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Registered: ‎11-09-2016

@syedz thanks,

i switch verbose and get detailed log.

You're right there are a lot of "removed nets"(maybe all of nets are removed).

I focused only optimization,performance side of my design. So maybe i left some of outputs driverless or loads.

Can you check attached verbose reports?

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berker_atel
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Registered: ‎11-09-2016

@yashp very good response,thanks.

Now i'll focus my coding.

 

 

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berker_atel
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Registered: ‎11-09-2016

Hi,

I only add vio debug cure to one questionable point of design when also optimization is enabled, it looks like place&route succesfull.

Dsp count was 16 when optimization disabled, it now 2, I guess this is due to optimization.

How has the effect the vio core? I'm confused.

 t3.png

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berker_atel
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5,324 Views
Registered: ‎11-09-2016

Hi,

The logic do nothing because output of logic don't go anywhere. Vivado thinks this logic unconnected and not used, it remove unnecesarry logic in optimization.

If anyone face the same problem, can check below link:

https://forums.xilinx.com/t5/Timing-Analysis/Hold-violation/m-p/798766#M12467

 

Thanks

View solution in original post

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queue1114
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Registered: ‎04-06-2012

As I am unable to create a new thread, this thread seemed to be the closest to what my question is:

 

I need to know the timing specifications of the IOBUFDS channels on the Artix 7 FPGAs. I have seached all over the Xilinx website, and come up with only blank screens when I click on a search result, although most of the time, there are no search results at all.

 

Does Xilinx actually publish timing specs for their products?

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