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Participant xilinxacct
Participant
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‘Killer’ designs - power & heat

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Is it theoretically possible to describe a circuit that will fit in available resources that will not be able to run due to not enough power within the FPGA (or does the power budget of the FPGA package already take that into account)?

 

And related to power is heat… is it theoretically possible to exceed the FPGAs ability to shed its heat, thus potentially damaging it (or are they thermally self-protecting/throttling OR does the implementer have to accommodate that in the design)?

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Historian
Historian
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Re: ‘Killer’ designs - power & heat

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How accurate is power estimator in Vivado?

 

As accurate as the data you give it. It can be used at various stages (or there is a different tool - I haven't used it for a while) even up to extracting data activity from a post-implementation netlist. But if you only "guesstimate" the device utilization and activity rates, the results can be pretty inaccurate.

 

Since you say there is no hardware mechanism that throttles (e.g. reduces clock speed), and I would need to provide such for potential high speed designs. As such, I suppose the hardware monitor would provide the temp info (and is accessible to the FPGA program).

 

So, yes... But the question almost makes no sense from an FPGA point of view. An FPGA is just an array of gates, and your clock is simply a pin that you bring in and manipulate with clock modifying blocks and buffer with clock networks. The device itself has no intelligence (outside the configuration controller) - everything post configuration is entirely under the control of the designer. If you want to implement some kind of temperature dependent clock gating, go ahead; design it, implement it (and test it). If you want to have a temperature controlled fan, then, again, go ahead - many designs do so. The only thing the FPGA supplies you with is an interface to the XADC (or power monitor) and the gate array (and I/O).

 

That being said, in a climate controlled environment, if one keeps to the power budget (and the FPGA is actively cooled; e.g. fan), one should be relatively safe, without having to actively manage clock/duty cycle, correct? 

 

It's impossible to answer this. Many (maybe even most) FPGA designs do not manage the clock frequency based on temperature. But, then again, most FPGA designs have fixed performance requirements - so you design the functionality with the performance you need and then you determine how big a heat sink, fan, (water cooling?) you need to keep the thing at the proper temperature (taking into account worst case ambient temperature).

 

But, yes, "reasonable" designs don't need to do power saving to keep cool, and reasonable designs only need reasonable air flow or small heat sinks; the BGA packages carry a fair amount of heat away from the die (both to the air and through the balls to the substrate/PCB).

 

Avrum

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Historian
Historian
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Re: ‘Killer’ designs - power & heat

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And related to power is heat… is it theoretically possible to exceed the FPGAs ability to shed its heat, thus potentially damaging it (or are they thermally self-protecting/throttling OR does the implementer have to accommodate that in the design)?

 

Absolutely!

 

It is the designer's responsibility to ensure that the die temperature of the FPGA remains below the maximum operating temperature. This temperature depends on the commercial grade (commercial, extended, industrial, and some other specialized grades). This is done by analyzing the power consumption of the design using the tools provided by Xilinx (the Xilinx Power Estimator spreadsheet).

 

Using this information, it is then up to the designer to determine if adequate cooling is provided based on ambient temperature, air flow, heat sinks, etc... If you don't manage the heat properly, your design will not work properly.

 

If you grossly underestimate power (or your cooling is grossly insufficient), then the temperature levels of the die can exceed the absolute maximum temperature specified for the device (specified in the datasheet). If this occurs you can damage the device; either slowly (over the long term) or even immediately (if the temperature rises high enough).

 

Is it theoretically possible to describe a circuit that will fit in available resources that will not be able to run due to not enough power within the FPGA

 

I'm not sure if this is possible. The current capabilites of the VCCINT and ground are probably sufficient to ensure that you run into the above problem before your core voltage starts to sag internally (assuming your power supply can supply the current).

 

For the I/O pins this is possible in the very short term - if you have a lot of high current output switching simultaneously in one bank it can cause a sag in the I/O supply voltage in that bank - this is due to the inductance of the power distribution network (which means that it cannot react instantaneously to a change in current demand). This is called SSO (simultaneously switching output) - the tools analyze SSO and report potential problems (this is a design rule check). Many of the newer I/O standards are low enough current to be immune to SSO problems - even high drive LVCMOS outputs with fast transitions can have an almost full bank of I/O without SSO problems.

 

Avrum

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Participant xilinxacct
Participant
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Re: ‘Killer’ designs - power & heat

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Great thanks... a few of follow-ups

 

How accurate is power estimator in Vivado? (e.g. how much margin should I add to be confident I don't drive it beyond its ability, OR has it already added that in the estimate)? The numbers I see so far are 'very' small.

 

Since you say there is no hardware mechanism that throttles (e.g. reduces clock speed), and I would need to provide such for potential high speed designs. As such, I suppose the hardware monitor would provide the temp info (and is accessible to the FPGA program).

 

That being said, in a climate controlled environment, if one keeps to the power budget (and the FPGA is actively cooled; e.g. fan), one should be relatively safe, without having to actively manage clock/duty cycle, correct? 

 

Thanks again

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Explorer
Explorer
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Re: ‘Killer’ designs - power & heat

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I remember an almost philosophical discussion about that long ago.

I believe you could fill the FPGA with all FFs toggling at the highest possible frequency and that would generate the maximum power.

 

Second question depends on the environment... in the very best conditions of heat sinking, theta(case-ambient) = 0 K/W so you can reckon the max power it can get rid of at the max Tj. Even though, it ultimately depends on ambient temp. Minimum, you know, -273C

Explorer
Explorer
466 Views

Re: ‘Killer’ designs - power & heat

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The problem of temp estimating in electronics is with air convection, even forced convection requires sophisticated FEM techniques to get an accurate figure that most of the times is better found (for cost, time and reliability) in the lab. 

Whatever the way you get your chip temperature, then there will be variations from unit to unit and with time (not all plastic china-made fans will give exactly the same air flow, air inlets get clogged with dust with time, etc). So the best approach for me is to use those estimations as a first approach for a first prototype with which figures will be adjusted (casing and other mechanical aspects, as well as other chips around and type of PCB, amount of copper and number of layers, come into play). Eventually you will need a margin that trades off the heat sinking cost and the number and cost of failures. That goes beyond of purely technical engineering and goes into economics.

My suggestion would be to use the internal temp sensor and shut it off if getting too hot, if that is possible to do. If computers do that, why not an embedded box?

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Historian
Historian
445 Views

Re: ‘Killer’ designs - power & heat

Jump to solution

How accurate is power estimator in Vivado?

 

As accurate as the data you give it. It can be used at various stages (or there is a different tool - I haven't used it for a while) even up to extracting data activity from a post-implementation netlist. But if you only "guesstimate" the device utilization and activity rates, the results can be pretty inaccurate.

 

Since you say there is no hardware mechanism that throttles (e.g. reduces clock speed), and I would need to provide such for potential high speed designs. As such, I suppose the hardware monitor would provide the temp info (and is accessible to the FPGA program).

 

So, yes... But the question almost makes no sense from an FPGA point of view. An FPGA is just an array of gates, and your clock is simply a pin that you bring in and manipulate with clock modifying blocks and buffer with clock networks. The device itself has no intelligence (outside the configuration controller) - everything post configuration is entirely under the control of the designer. If you want to implement some kind of temperature dependent clock gating, go ahead; design it, implement it (and test it). If you want to have a temperature controlled fan, then, again, go ahead - many designs do so. The only thing the FPGA supplies you with is an interface to the XADC (or power monitor) and the gate array (and I/O).

 

That being said, in a climate controlled environment, if one keeps to the power budget (and the FPGA is actively cooled; e.g. fan), one should be relatively safe, without having to actively manage clock/duty cycle, correct? 

 

It's impossible to answer this. Many (maybe even most) FPGA designs do not manage the clock frequency based on temperature. But, then again, most FPGA designs have fixed performance requirements - so you design the functionality with the performance you need and then you determine how big a heat sink, fan, (water cooling?) you need to keep the thing at the proper temperature (taking into account worst case ambient temperature).

 

But, yes, "reasonable" designs don't need to do power saving to keep cool, and reasonable designs only need reasonable air flow or small heat sinks; the BGA packages carry a fair amount of heat away from the die (both to the air and through the balls to the substrate/PCB).

 

Avrum

315 Views

Re: ‘Killer’ designs - power & heat

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And related to power is heat… is it theoretically possible to exceed the FPGAs ability to shed its heat, thus potentially damaging it (or are they thermally self-protecting/throttling OR does the implementer have to accommodate that in the design)?

 

The FPGAs contain a temperature sensor.  (I think in all cases they have 1 sensor / die, so there will be multiple sensors in a multi-die package.)  The output of the sensor is available to the FPGA fabric, both as a "number" indicating temperature, as well as some flags that indicate (user settable) thresholds.

Reference: UG580

 

Some of my products have larger FPGAs that require heatpipes and radiators with forced airflow to stay cool.  Some of the mandatory safety (e.g. UL) tests will involve blocking the air vents or seizing the fans to determine whether the product is safe under those conditions.  The design must take that into account.

 

My designs use one of the flags on the temperature sensor (typically set to come on at well under 125 degree C) to reduce power consumption to stop the FPGA from being damaged.  Whilst I could reduce the power consumption by turning off clocks (with e.g. BUFGCE), I find it more useful to gate the datapath in some way to reduce the number of transitions.  E.g. in an Ethernet gizmo in which most of the heat comes from packet processing, I can stop packets at the receive MAC.  This leaves the rest of the datapath "up" which means my management software won't crash, allowing the product to recover gracefully from the overtemperature event.  N.B. the crashing problem will be particularly bad if you use PCIe - whilst the PCIe spec. describes hot swap in detail, in practice you'll find that your OS will crash if an endpoint suddenly disappears.

 

EDIT:

(from UG580, etc.) it is possible to include a flag in the bitstream to cause the FPGA to shut down (i.e. lose configuration) automatically at some temperature.  I've never used this, but it might work for you.

 

Also bear in mind that the FPGA is probably surrounded on the PCB by a sea of capacitors that will be heated by the FPGA.  Some of these capacitors (the non-MLCC ones) might start to be damaged at lower temperatures than the FPGA.  Actually, for some types of caps, it behaves like a diffusion limited wearout mechanism - the lifetime is specified as so many hours at some temperature, and the lifetime will decrease exponentially with increasing temperature.

Adventurer
Adventurer
119 Views

Re: ‘Killer’ designs - power & heat

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"Is it theoretically possible to describe a circuit that will fit in available resources that will not be able to run due to not enough power within the FPGA?"

Yes.  In fact, if you create a shift register of ALL DFF (or more than 80% of them) and shift a 0101.. into them (say at 100 MHz), the device will require so much current, the voltage will droop, and the device will reset due to POR tripping.  So it isn't theoretical -- it can happen.

Of course, the power estimate will give you a clue this is not a good idea.

I have seen designs where the value of the data being processed tripped POR.  These were cases where the power system was definitely not designed for the maximum possible load (and neither was the cooling solution).

l.e.o.

 

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