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a707
Visitor
Visitor
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Registered: ‎04-04-2011

Measuring the Pulse Width

Hi

 

Can someone help me with the following description of measuring the pulse width by using a state diagram. I have created the state diagram with two states, however i am having trouble working out how would i wait until the next rising edge is being detected.

 

 

1.  waiting for leading edge of pulse, keep counter reset

2.  pulse started, let counter increment until pulse trailing edge detected

3.  pulse ended, freeze counter (or take a snapshot of counter value)

4.  loop back to state #1

 

 

 

Note this was taken from another thread about pulse width.

 

This is the state diagram i have done but as i said before i'm having trouble with step 2) of it.

 

P.S

statemachine.JPG
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16 Replies
sonicwave
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Registered: ‎11-26-2008

Stay in "High" as long as pulse='1', and do the transition to "Low" when pulse='0' ?

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a707
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Registered: ‎04-04-2011

That would not work becuase  if the pulse from high then low it should stay counting until the next rising edge is high.

 

for instance the pulse may be something like this

     first rising edge                                      second rising edge

        --------------                                            ----------------------

------                   --------------------------------

 

The width is between the first and second.

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eteam00
Instructor
Instructor
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Registered: ‎07-21-2009

 

reg [1:0]  insync;            // synchronise async pulse input
reg [15:0] pw_ctr, pw_save;   // pulse width counter, plus snapshot copy

always @(posedge clock)
  insync  <=  {insync[0], pulse_input};  // sync the async pulse input

always @(posedge clock)
   case (insync[1])
     1'b0:                       // state #1 and #2: pulse input is '0'
       begin
         pw_save  <=  pw_ctr;    // save the last pulse width count
         if (insync[0] == 1)     // state #2: is pulse input going high?
            pw_ctr <= 16'h0000;  // yes, clear the pulse width counter
       end

     1'b1:                       // state #3: pulse input is '1'
         pw_ctr <= pw_ctr + 1;   // count while pulse input is '1'

   endcase

Technically, there are three states:

1.  Input is low, and staying low

2.  Input is low, but about to go high

3.  Input is high

You need 3 states to

  • clear the counter
  • allow the counter to increment
  • save the counter value when counter is neither clearing or counting

If you don't need to save a copy of the counter in a snapshot register, then you only need 2 states.

 

There are many many ways of coding this problem.  This is just one example.

 

-- Bob Elkind

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a707
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Registered: ‎04-04-2011

suppose i just have two states according to your explaination when i don't need to take the snapshot then the ??? will be pulse='1'/c++ and pulse='0'/c=0

 

Also what language is your code in?

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eteam00
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Registered: ‎07-21-2009

suppose i just have two states according to your explaination when i don't need to take the snapshot then the ??? will be pulse='1'/c++ and pulse='0'/c=0

Agreed, only two states needed in the example you describe, exactly as you describe them.

Also what language is your code in?

Verilog.

 

-- Bob Elkind

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a707
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Registered: ‎04-04-2011

I am still unable to understand how that would work, because i am finding the width of the pulse, if the pulse went low it should still measure the value of that until the next rising edge when pulse is high. Like what i drew before

 

    first rising edge                                      second rising edge

        --------------                                            ----------------------

------                   --------------------------------                

        <------------------------Pulse Width-------------->     

 

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sonicwave
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Registered: ‎11-26-2008

 


@a707 wrote:

That would not work becuase  if the pulse from high then low it should stay counting until the next rising edge is high.

...


 

Ah - so you are not measuring the pulse width, but rather the period of the signal...

 

And also, the code posted by Bob previously does almost what you want - it should be simple to modify it to also count when the input signal is low...

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a707
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Registered: ‎04-04-2011

Can anyone convert that code to Verilog? becuase i normally work in VHDL

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eilert
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Registered: ‎08-14-2007

Hi,

you probably mean covert to VHDL, because it is already in verilog.

 

It's not so hard:

For each "always@(posedge clock)"

you create a clocked process.

The case is almost like in VHDL.

  1'b0 means '0'

  1'b1 means '1'

16'h0000 is X"0000"

declared either as std_logic(15 downto 0) or unsigned (15 downto 0)

 

So you should be able to do the conversion yourself in a few minutes.

 

Have a nice synthesis

  Eilert

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a707
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Registered: ‎04-04-2011

So if i was measuring the period of the signal, would the state diagram be different?

for example instead of pulse = '1'/c++ and pulse = '0' /c=0

would it work if i make it: pulse <= pulse + '1' / c++ and pulse <= pulse + '0' / value<=c in order to measure the period?
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eteam00
Instructor
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Registered: ‎07-21-2009

So if i was measuring the period of the signal, would the state diagram be different?

Your logic becomes simpler, you have only one event to detect

 

reg [1:0]  insync;            // synchronise async pulse input
reg [15:0] pw_ctr, pw_save;   // pulse width counter, plus snapshot copy

always @(posedge clock)
  insync  <=  {insync[0], pulse_input};  // sync the async pulse input

always @(posedge clock)
  if (insync == 2'b01)       // state #1: detect input rising edge, beginning a new pulse cycle
    begin
      pw_save  <= pw_ctr     // save snapshot of the current cycle period
pw_ctr <= 16'h0000; // init counter to '0' or to '1', your choice end else // state #2: not state #1 pw_ctr <= pw_ctr + 1; // count until next cycle begins

Technically, there are two states:

1.  Input is low and about to go high

2.  Input is not low or not about to go high

You need 2 states to

  • save the counter value and clear the counter
  • allow the counter to increment

-- Bob Elkind

rising edge of input
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a707
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so this would be incorrect?

pulse <= pulse + '1' / c++ and pulse <= pulse + '0' / value<=c

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eteam00
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Registered: ‎07-21-2009

so this would be incorrect?
pulse <= pulse + '1' / c++ and pulse + '0''  / value<=c

I hesitate to answer without a clear understanding of the syntax (or language) you are using.
Would you translate to plain English language text, or point me to a reference manual for the language you are using?

-- Bob Elkind

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Summary:
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2. Search the forums (and search the web) for similar topics.
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a707
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Registered: ‎04-04-2011

i am using a state diagram to depict the states, like the one in my first post.

 

Firstly in State 1

- when pulse is 0 then count remain at 0    (pulse = '0' / c=0)

- when pulse is 1 then count start incrementing (pulse = '1' / c++)

 

Secondly in State 2

This is where i am stuck on

 

- it should first contuine counting until it sees the next rising edge ( ??????/ c++)

- it should return back to State 1 when a rising edge is detected, hence the count value will be saved. (pulse = done / value <= c)

 

my problem is trying to translate this into State diagram representation

I hope my problem now is much clearer

 

 

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eteam00
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Registered: ‎07-21-2009

Thank you for the translation.

Firstly in State 1

- when pulse is 0 then count remain at 0    (pulse = '0' / c=0)

- when pulse is 1 then count start incrementing (pulse = '1' / c++)

You have described two states, correct?  State 1: [pulse is '0'] and State 2: [pulse is '1'].

Secondly in State 2  This is where i am stuck on

- it should first contuine counting until it sees the next rising edge ( ??????/ c++)

- it should return back to State 1 when a rising edge is detected, hence the count value will be saved. (pulse = done / value <= c)

How can a state return to State 1 on a detection of a rising edge, if State 1 is for (pulse = '0') ?

I think you are describing two different states, one which detects a rising edge and one which detects a falling edge

 

I think you (or maybe it's me) are confused.  Here is an alternate state diagram.  Does this make sense?

+-->  State 1  -------------->  State 2   ------------>  State 3 ---------------+

|     pulse is '0'              pulse is '1'             pulse is '1'           |

|     no pulse counting         (single cycle)           increment pulse count  |

|     save count value          init count value                                |
|
                                                                               |

+-------------------------------------------------------------------------------+

Did I get this right?  Does this make sense?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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a707
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Registered: ‎04-04-2011

no i think your first solution with 2 states were correct.
I'm the one that was confused hence it confused you.
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