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princemmf
Visitor
Visitor
3,631 Views
Registered: ‎05-18-2009

Middle states at transition moment

I implemented a 16-bit register to generate required data in my design. It should change from x”0000” to x”FFFF” at the rising edge of the global clock. I did the post-route simulation, finding out that at the rising edge there are a lot of middle states between x”0000” and x”FFFF”. This is causing a great trouble in my design. In the attachment is the picture showing specified waveforms!

 

How can I solve this problem?Thank you for your kind attention! 

 

Prince Ma,

Harbin Institute of Technology,

P.R.China,

June.3rd.2009

waveforms.JPG
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2 Replies
jprovidenza
Voyager
Voyager
3,620 Views
Registered: ‎08-30-2007

Briefly - you can't solve this problem.

 

In the real world, ie, post-route, the output of each flip flop follows a different routing path

to its destinations.  You can imagine that output Q1 drives input D1 and Q2 drives D2. Since

Q1, Q2, D1, and D2 are located in physically different locations on the silicon, the distances

between them are different.  Thus, if both Q1 and Q2 switch at the same time, D1 and D2

will see their inputs change at slightly different times due to the different routing delays.

 

In a synchronous design, as long as the routing delays are relatively small compared to the

clock period and setup/hold times, everything works fine.  If the routing delays become too

long, the design fails.

 

If you are decoding the bus value and using that to clock more logic, you've got a fundamentally

flawed design - you will probably have decode glitches.

 

On common technique used to work around this is to use Gray Coding - by design, only one

bit is allowed to change on each cycle.  This is an excellent way to avoid this problem and to

pass counter values from one clock domain to another.

 

Hope this helps!

 

John Providenza

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mcgett
Xilinx Employee
Xilinx Employee
3,619 Views
Registered: ‎01-03-2008

What you are seeing is normal for any FPGA or ASIC.  The differences in the transitions across the 16 bit bus is simply do to clock skew and net propogation delays (mostly net delays).

 

Timing analysis will guarantee that all of the propogation delays will meet the necessary set up and hold times to the next register in a synchronous system.

 

If you are transferring the data bus from one clock domain to another then you need a synchronizer circuit to ensure that all of the data has settled first before it is clocked into the next clock domain.

 

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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