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j.rivas.prieto
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Registered: ‎12-07-2009

Modifying parameters of a System Generator design while it is running.

Hi all,

 

I am working with a custom board which has a Virtex-4 FX100. Inside, there is a VHDL-based framework which interfaces the different parts on the custom board with the "DSP core", which is developed under System Generator. In this System Generator design, there are some variables that I would like to change while the FPGA is running. For instance, it would be desirable being able to modify the length of a particular ASR, or control a multiplexer to select different channels manually, from the "outside world". Which is the common approach to modify those parameters while the design is running?

 

As I will have to output some data after this DSP core I was thinking on ChipScope, can it be used to modify the parameters on the design as well?. I have read about Hardware co-simulation, but I don't know if that is really what I am looking for, as the SysGen design is not the top level in the whole design. Also, the frequency of this design is 312 MHz, which may have an influence on the chosen solution to modify the parameters.

 

Regards,

 

Jorge

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ddemmin
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Registered: ‎02-10-2009

What kind of external interface do you have? A serial port is about the simplest you can get if you are looking for ideas.

 

I dont think chipscope is what you are looking for.

 

You can implement an address and data bus within sysgen and interface it to a serial port with a simple message protocol.

 

You can also implement the address and data bus within the HDL fabric and connect it via dedicated signals that are brought out of the core.

 

What kind of response time do you need/expect when you are modifying the parameters of the core?

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j.rivas.prieto
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Registered: ‎12-07-2009

I have both a serial port and a JTAG connector. The serial port library is on the VHDL framework, but I think it could be modified in order to interface with the sysgen core. Do you know if using hardware co-simulation is possible when using the sysgen core embedded on a bigger system?

 

The response time is not critical. I just need it to change, don't mind if it takes even a couple of seconds.

 

Thanks for the input, I was expecting something more difficult than just a simple serial port, I didn't think about that :)

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