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Participant gkillua36
Participant
5,167 Views
Registered: ‎09-02-2016

No response from XPS system cache with generic AXI interconnect

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Hello, everyone.

 

Currently I am trying to use the system cache IP in XPS with ISE 14.7 for external connection with FPGA logic with AXI interconnect. What I am doing is as follows:

 1. Add a system cache IP, configure with one generic AXI slave port, one AXI master for connecting main memory.

 2. Add a BRAM controller and also a BRAM. Both are dual port and connect the port A and B correspondingly.

 3. Add AXI interconnect, connect the system cache master AXI and BRAM controller slave port.

 4. Add external master so as to output the MAXI port out of XPS.

 5. Add another AXI interconnect, connect the external MAXI with system cache generic SAXI.

 6. Modify the address for both memory controller and system cache to be in same range, as suggested by the product guide.

 7. Output ports for both ACLK, ARESETN and MAXI external ports.

 8. Go back to ISE, generate top module for XPS and add stimulus in the testbench for simulation. The stimulus for AXI is tested successfully with other applications. 

 

When I test writing to the cache, I can successfully get feedback with "AWREADY" "WREADY" .However, I observe that in the simulation, the write response signal "BVALID" is always set as zero. It is supposed to response to my writing request in AXI protocol. I cannot fix this problem even in Vivado. Here I show the simulation waveform with "BVALID" distinguished in yellow. 

 

Is it possible that the cache access from AXI is different from general AXI? If so, how can I get details about it? 

I fail to find the example code for testing the system cache from Xilinx and I am not sure whether this exists. If anyone find it please tell me.

 

Thanks for everyone who attempt to help me. 

No response of bvalid.JPG
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1 Solution

Accepted Solutions
Adventurer
Adventurer
9,541 Views
Registered: ‎08-24-2008

Re: No response from XPS system cache with generic AXI interconnect

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The slave is not responding properly. If you see the signalling diagram from an AXI write transaction in the relevant documentation, you will notice this difference. In your case, most likely, you have not run the simulation long enough to see any proper response from the slave side. Try simulating your design for a longer period of time.

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2 Replies
Adventurer
Adventurer
9,542 Views
Registered: ‎08-24-2008

Re: No response from XPS system cache with generic AXI interconnect

Jump to solution

The slave is not responding properly. If you see the signalling diagram from an AXI write transaction in the relevant documentation, you will notice this difference. In your case, most likely, you have not run the simulation long enough to see any proper response from the slave side. Try simulating your design for a longer period of time.

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Participant gkillua36
Participant
4,983 Views
Registered: ‎09-02-2016

Re: No response from XPS system cache with generic AXI interconnect

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Thanks, Sharad
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