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Explorer
Explorer
8,252 Views
Registered: ‎08-23-2011

OFFSET IN timing constraints between 2 FPGAs

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hi,

 

i have a design where i have connected 2 FPGAs - a vlx75T (which sends a 125MHz clk and txdata) to a vlx760 FPGA. and the vlx760 FPGA sends back data (rxdata) to vlx75T at the same clk generated by vlx75. there is connector in fpga_setup.png

between the FPGAs to connect them. I wanted to know -

 

1) is it  "compulsary" to add offset in constraints for the txdata and clk lines going into the vlx760t FPGA? or even without the offset in constraint, the design can still work?

 

 

2)My thinking is that since the clk and txdata are coming from the same source and have the same path/interconnect delay so in that case the clk and txdata going into the vlx760 FPGA donot need offset in constraint as the delay on both the lines will be the same. is my understanding correct?

If my understanding is not correct, then in what case will i need to use the offset in/out constraints?

 

3) do i need offset out constraint for the rxdata going from vlx760 to vlx75 fpga?

 

4) since the clk is 125MHz, the design is failing to meet timing on the vlx760 fpga. will adding the offset in/out constraints to vlx760 fpga - IN ANY WAY - help meet the 125MHz period constraint ?

 

help !!! :)

 

z.

 

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1 Solution

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Explorer
Explorer
15,191 Views
Registered: ‎09-16-2010

Re: OFFSET IN timing constraints between 2 FPGAs

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The offset in/out constraints are not used by the ISE tools to change the placement or routing in any way. They just tell you if you met your expected in/out timing or not. They are not required but if understood correctly can give you valuable feedback. if you pay close attention to the internals of the design you probably don't need them. Just look in fpga editor to see exactly what's going on internally. Make sure to register your io in the iobs to get more consistent results. You should try to meet timing first without those offset in/out constraints and then add them in later to make the design solid across builds.
Andrew

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1 Reply
Explorer
Explorer
15,192 Views
Registered: ‎09-16-2010

Re: OFFSET IN timing constraints between 2 FPGAs

Jump to solution
The offset in/out constraints are not used by the ISE tools to change the placement or routing in any way. They just tell you if you met your expected in/out timing or not. They are not required but if understood correctly can give you valuable feedback. if you pay close attention to the internals of the design you probably don't need them. Just look in fpga editor to see exactly what's going on internally. Make sure to register your io in the iobs to get more consistent results. You should try to meet timing first without those offset in/out constraints and then add them in later to make the design solid across builds.
Andrew

View solution in original post