06-03-2010 12:42 PM
It appears a rather strange problem to me. I am using a variable-length RAM-based shift register (.xco and .vhd files attached) which has the usual input, output, clock and sclr ports. When I simulate this model in ModelSim, I see that the output is not aligned with the clock: It appears after some delay from the riding edge of the clock signal. This delay is not even some integer multiple of clock periods. Curiously, this problem doesn;t occur in another simulation of a RAM-based shift register which is of smaller depths (say, 16 words) than the current one (= 1024 words).
I am using Xilinx ISE 11.4 and targeting my design on Virtex 5 SXT95.
So what could be going wrong here? Any help would be greatly appreciated.
Kumar Vijay Mishra.
06-03-2010 12:43 PM
06-03-2010 01:31 PM
I don't understand why you think that this is strange. In real life (and a good simulation) events are not simultaneous. The clock edge happens and then results appears after a small delay.
06-03-2010 01:59 PM
It is strange because (a) this doesn't happen when I simulate a shift-register of smaller depth, say 64 words and (b) this is a functional simulation which should not show the "real-life" delays.
06-03-2010 04:08 PM
There are likely different architectures in your 16 deep version versus the 1024 deep version resulting in different simulation models. The larger model evidently is adding unit delays on the clock-to-out, a good practice IMHO, while the smaller model skipped this. Functional simulations can and do include delays. If you take a look at the Xilinx UNISIMS libraries you will see small unit delays included in most of the sequential elements.
In any case the small delay for clock-to-out on the shift register isn't an issue.
06-18-2010 12:03 PM
Also, I was wondering if it is possible to implement these shift registers using DSP48Es? Is there a reference deisgn available for the same?
Kumar Vijay Mishra.