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Explorer
Explorer
7,914 Views
Registered: ‎08-23-2011

PCIe on virtex6 using high speed io card (XAPP1022)

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hi,

 

i was trying to implement PCIe (gen2) on fpgas and i was facing some issues in what all blocks/cores i need. here is what i have -

 

i have a virtex6 xc6vlx75t fpga. this is a high speed i/o card (daughter card), which comes with a virtex6 vlx760 fpga.

i read in the xapp1022 that we can use logicore to make a pcie block for the virtex6 devices. this is an integrated block for pcie express.

 

i wanted to know that when i generate this core, then does it create a MAC, a controller or a PHY for the PCIe?

 

looking at the manuals, i understand that this pcie core would go onto the daughter card vlx75t. is that all i need on this high speed io card or do i need to put the pcie controller onto this card as well?

 

what core/modules should i have on the main virtex6 vlx760 fpga?

 

where does the PHY go in all this? do i even need it if i am implementing the pcie core using logicore?

 

please let me know ...

 

z.

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Scholar
Scholar
12,615 Views
Registered: ‎02-03-2010

Re: PCIe on virtex6 using high speed io card (XAPP1022)

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Hi ,

 

From your earluer post i understand that you wanted to validate your PCIe controller which has Datalink and transaction layers with pipe interface towards phy side.

 

In this way you need to use the GT wizard core and choose the PCIe protocol templete to generate the phy files.

The GT wizard generated files will give you pipe interface and you can connect this to Datalink layetr of your  custom core and implemet the PCIe endpoint/Root as whole.

 

 

Regards,.

KR

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Teacher
Teacher
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Registered: ‎03-31-2012

Re: PCIe on virtex6 using high speed io card (XAPP1022)

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In pcie stack there is no MAC per se. I believe the core you get from Xilinx is a link layer controller and a PHY, most of which is built into the hardware, not made from fabric.
You create the pcie ip for xc6vlx75t (which has the transceiver for pcie as it ends with t) and talk to the rest of the pcie system through this fpga where as your main system lives on the 760 device.
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Scholar
Scholar
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Registered: ‎02-03-2010

Re: PCIe on virtex6 using high speed io card (XAPP1022)

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Hi ,

 

When you generate Virtex-6 Integrated block fro PCI Express, the core includes PHY + Link layer and Transaction layer of the PCIe protocol.

The core files wrap both PHY and Hard block of the PCIe core(LL+Transactionlayer) .

PHY part includes MGT block with some logic for resets and other logic .

 

The Xapp 1022 will have a PIO design over the core which is Application logic. This contains some BRAM blocks and a PC side driver is provided which can communicate PC to the application logic of the PCIe core.

 

I hope this clears your doubt.

 

Regards,

KR

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Explorer
Explorer
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Registered: ‎08-23-2011

Re: PCIe on virtex6 using high speed io card (XAPP1022)

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hi,

 

yes this does clear some of my doubts. but i have a few more queries -

 

like you said - the xilinx pcie logic core generated by coregen implements the PHY and LL and transaction layer.

and on top of that you have the pio design which is the user application.

 

however, if i have my own pcie IP (which has the phy, controller blocks, user application etc.), then do i still need the pcie logicore to interact with my pcie IP in some way to implement/emulate pcie on fpga?

 

or is the pcie logicore used when the PHY etc. are not available?

 

also - when we say the PHY is bundled into the logicore, then does it mean that when you synthesize the core, then some of the IO pins are configured so that they can work with the PHY core? or does it happen in some other manner?

 

from my understanding, PHY is a kind of chip/core that converts analog to digital ... correct? so if that is the case, then does the pcie logicore have this type of a PHY and its being implemented on the bit file and some of the I/O pins are being used for the PHY connection to the outside- is my understanding correct? or is something else happeing w.r.t. implementing the PHY?

 

i am targetting a virtex6 xcvlx75t fpga - so does it support pcie phy on the fabric???

 

please let me know ...

 

z. 

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Scholar
Scholar
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Registered: ‎02-03-2010

Re: PCIe on virtex6 using high speed io card (XAPP1022)

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Hi ,

 

From your earluer post i understand that you wanted to validate your PCIe controller which has Datalink and transaction layers with pipe interface towards phy side.

 

In this way you need to use the GT wizard core and choose the PCIe protocol templete to generate the phy files.

The GT wizard generated files will give you pipe interface and you can connect this to Datalink layetr of your  custom core and implemet the PCIe endpoint/Root as whole.

 

 

Regards,.

KR

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Explorer
Explorer
7,765 Views
Registered: ‎08-23-2011

Re: PCIe on virtex6 using high speed io card (XAPP1022)

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hi KR,

 

thanks for the reply.

 

you are correct that I want to to validate PCIe controller that resides on my main FPGA with PIPE interface towards the PHY side. and the phy is implemented on the daughter fpga (lx75t), using xilinx PCIe logicore coregen tool.

 

however when i do generate the core, it comes up with AXI-S interface and not the PIPE interface.

 

even the document -  logicore IP virtex-6 integrated block v2.5 for pcie express says the supported user interfaece is AXI-4 Stream interface.

 

So my questions are -

1) can the logicore IP virtex-6 integrated block v2.5 for pcie express be generated/configured in any way for PIPE interface?

2) you mention the GT wizard ... is this different from the logicore IP virtex-6 integrated block v2.5 for pcie express block? and is it generated using coregen or something else? and does it support PIPE interface to connect to my controller?

 

please let me know ...

 

z.

 

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Explorer
Explorer
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Registered: ‎08-23-2011

Re: PCIe on virtex6 using high speed io card (XAPP1022)

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Thanks KR .... this would be the solution I am looking for - PIPE interface to connect to the GTX trancievers using my PCIe controller.

more questions regarding this approach in another thread ...
thanks again!
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