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Newbie
Newbie
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Registered: ‎09-29-2009

Package up VHDL and Xilinx Cores in to a single Core

Hi there,

 

Is it possible to package up preject source (VHDL and XCO files) in to a single output file? Synthesis of our design produces an NGC file, but when this is added to another project, it requires all the Xilinx Coregen components (as NGC's) to be added to the projects in order to build properly. What I'm really looking for is an output format that we can deliver to our customer that can be integrated in to their design that is a black box and ideally a single file.

 

Many Thanks

 

Toby

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