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Visitor efaz
Registered: ‎02-01-2016

Partial Reconfiguration: Measuring Zynq PCAP Reconfiguration Time

Hi everybody,
I started to analyze the performance of a software application which is able to partially reconfigure the Zynq Programmable Logic using the PCAP interface.
I basically added some lines of code to the function I'm using to load a partial bitstream from the DDR memory into the PL, "XDcfg_TransferBitfile", to measure how much time it takes to load a new partial bitstream. I'm copying the code below. 

int XDcfg_TransferBitfile(XDcfg *DcfgInstPtr, int PartialCfg, u32 PartialAddress, u32 bitfile_length_words)
    u32 IntrStsReg = 0;
    float elapsed_time; //[us]
    int bitstream_dimension; //[kB]
    float avg_throughput; //[MB/s]


    XDcfg_Transfer(DcfgInstPtr, (u8 *)PartialAddress, bitfile_length_words,

    // Poll IXR_DMA_DONE
    IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
    while ((IntrStsReg & XDCFG_IXR_DMA_DONE_MASK) !=
            XDCFG_IXR_DMA_DONE_MASK) {
        IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);

    if (PartialCfg) {
        /* Poll IXR_D_P_DONE */
        while ((IntrStsReg & XDCFG_IXR_D_P_DONE_MASK) !=
                XDCFG_IXR_D_P_DONE_MASK) {
            IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
    } else {
        /* Poll IXR_PCFG_DONE */
        while ((IntrStsReg & XDCFG_IXR_PCFG_DONE_MASK) !=
                XDCFG_IXR_PCFG_DONE_MASK) {
            IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
        // Enable the level-shifters from PS to PL.
        Xil_Out32(SLCR_LVL_SHFTR_EN, 0xF);
        Xil_Out32(SLCR_LOCK, SLCR_LOCK_VAL);


    elapsed_time = 1.0 * (tEnd - tStart) /(COUNTS_PER_SECOND/1000000);
    bitstream_dimension = bitfile_length_words*4/1000;
    avg_throughput = (bitstream_dimension / elapsed_time) * 1000.0;

    printf("Partial Reconfiguration took %.3fus\nBitstream dimension: %dKB\nAverage throughput: %fMB/s\n",
                               elapsed_time, bitstream_dimension, avg_throughput);

    return XST_SUCCESS;

The code above seems to work but I'm reading strange numbers:

-when I load for the first time a reconfigurable module the throughput is around 130MB/s, which is reasonable

-for the following reconfigurations of the reconfigurable module, however, the throughput goes up to almost 200GB/s

What am I doing wrong about the time measurements?


Thanks in advance

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2 Replies
Visitor sdu_liuke
Registered: ‎03-20-2017

Re: Partial Reconfiguration: Measuring Zynq PCAP Reconfiguration Time

Hello,  efaz,  I met the same condition while trying  the example from Unversity Program(Lab3 reconfig_peripheral_lab):

  • Only the first time , the throughput is around 130MB/s, which is reasonable refer to UG585(145MB/s).  
  • Other times, 109KB bitfile only costs about 5us, more than 190GB/s. 

Why? May be caching ? or just programme the bit which is needed to be flip, which means ,in the LAB3,just 5us*130MB = 650*8 bit  are different?


Waiting for your answers, Thanks!

Have fun with FPGA
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Visitor sdu_liuke
Registered: ‎03-20-2017

Re: Partial Reconfiguration: Measuring Zynq PCAP Reconfiguration Time

a small mistake : the throughput is 109KB / 5us = 20GB/s after first partial reconfiguration(109KB, 890us). Sorry

Have fun with FPGA
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