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Adventurer
Adventurer
3,931 Views
Registered: ‎11-28-2009

Phase matched external signal and internal clock

I need to generate an FPGA internal clock that is phase matched
to an external signal.  By phase matched I mean that the relative
phase of the external signal and the internal clock is known and stable.

 

There is evidence that this is an intended usage model for the PLL in
V5/6.  The V6 clocking guide it says:

 

IBUFG - Global clock input buffer, the MMCM will compensate the delay of this path.

 

And in many places we see a BUFG used as feedback to the PLL.

 

Hence, it appears this is an intended usage model.

 

However... the information necessary to support such a usage ends there.  I can
find no timing specs for an IBUFG(DS).  If I run the timing analyzer on this circuit,
the timing analyzer uses a standard tIOPI for the IBUFGDS and standard delays
for the BUFG and its network.

 

Is there some special mode for the timing tools to understand "PLL magic"?  Am I
missing something here?

 

Thanks in advance.

 

Leith Johnson

 

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Xilinx Employee
Xilinx Employee
3,927 Views
Registered: ‎01-03-2008

Yes, the standard delays for the IBUFG and the BUFG will be present in the timing reports, but these will be offset with a negative delay through the MMCM.
------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Teacher
Teacher
3,891 Views
Registered: ‎07-09-2009

Hi

 

have you tried the coregen ?

  that I think has a clock core for doing this !

 

 It's a little old, but XAPP132 is the basis you need.

 

http://www.xilinx.com/support/documentation/application_notes/xapp132.pdf

 

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