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Teacher xilinxacct
Teacher
755 Views
Registered: ‎10-23-2018

Pro/Cons of pure combinational logic solutions

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When you have the luxury of algorithmically being able to implement a solution purely with LUTs, no clocked logic ‘required’, is there any specific downside or benefit for choosing the option, such as power, heat, real estate, etc…

 

Speaking of power, would there be a material difference of enabling/disabling the logic when using? e.g. place some data on a bus, enable the function, output appears of a bus, get result, disable the logic.

 

A benefit would seem to be the timing of a single execution would seem to be as fast as possible, as it only involves the propagation delay of the worst path. Although, in the same vein, ‘if’ the algorithm could be parallelized by adding clocked logic, it is conceivable the overall throughput could be potentially be increased with the extra complexity.

 

I would be interested in hearing your thoughts.

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712 Views
Registered: ‎01-22-2015

Re: Pro/Cons of pure combinational logic solutions

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@xilinxacct

 

     …no clocked logic ‘required’…

If an author tears apart the pages of his book and throws the words at you in random order (ie. with different propagation delay) then the book will make no sense to you. The book only makes sense when the author uses the rules of grammar to arrange his words into sentences, paragraphs, and pages. In the FPGA world, registers and clocks (the rules of grammer) are usually* required to help us overcome the confusion caused by different propagation delays for combinational logic signals (the words).

 

Of course, there are tradeoffs. Adding registers and clocks to the combinational logic (ie. using clocked-logic aka sequential-logic) increases electrical power consumption. The graph below is from the Texas Instruments venerable 74LVC374 digital register IC. Note how supply current, Icc, drawn by the register increases with frequency of the clock input to the register - even if the register is essentially doing nothing (ie. the D-input to the register is constant).  For example, at a supply voltage of 3.3V, electrical power consumed by the register ranges from near nothing at 0Hz to 18mA*3.3V=0.06W at 100MHz. -and there are many many registers inside the FPGA.

74LVC374_power.jpg

 

     …would there be a material difference of enabling/disabling the logic..

My iPhone does this all the time to get the most battery-life.  In FPGAs you can do clock gating (essentially turning clocks ON/OFF) to save power.  However, here again there are tradeoffs as explained in <this> post by avrumw and others.

 

Mark

 

*edit 03Nov18

View solution in original post

3 Replies
713 Views
Registered: ‎01-22-2015

Re: Pro/Cons of pure combinational logic solutions

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@xilinxacct

 

     …no clocked logic ‘required’…

If an author tears apart the pages of his book and throws the words at you in random order (ie. with different propagation delay) then the book will make no sense to you. The book only makes sense when the author uses the rules of grammar to arrange his words into sentences, paragraphs, and pages. In the FPGA world, registers and clocks (the rules of grammer) are usually* required to help us overcome the confusion caused by different propagation delays for combinational logic signals (the words).

 

Of course, there are tradeoffs. Adding registers and clocks to the combinational logic (ie. using clocked-logic aka sequential-logic) increases electrical power consumption. The graph below is from the Texas Instruments venerable 74LVC374 digital register IC. Note how supply current, Icc, drawn by the register increases with frequency of the clock input to the register - even if the register is essentially doing nothing (ie. the D-input to the register is constant).  For example, at a supply voltage of 3.3V, electrical power consumed by the register ranges from near nothing at 0Hz to 18mA*3.3V=0.06W at 100MHz. -and there are many many registers inside the FPGA.

74LVC374_power.jpg

 

     …would there be a material difference of enabling/disabling the logic..

My iPhone does this all the time to get the most battery-life.  In FPGAs you can do clock gating (essentially turning clocks ON/OFF) to save power.  However, here again there are tradeoffs as explained in <this> post by avrumw and others.

 

Mark

 

*edit 03Nov18

View solution in original post

Teacher xilinxacct
Teacher
703 Views
Registered: ‎10-23-2018

Re: Pro/Cons of pure combinational logic solutions

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On your first part of the reply... Of course 'most' complex FPGA design 'require' clocking... I was speaking of the special cases in which pure computational logic is sufficient. (e.g. a 'pattern' is presented as inputs as the cascade of logic results in 'pattern' being present as output). They are deterministic if you know 'when' you can look for the stable answer.

 

So, yes, I totally agree... and as Einstein would say... Everything should be made as simple as possible, but not simpler. :-)

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Scholar u4223374
Scholar
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Registered: ‎04-26-2015

Re: Pro/Cons of pure combinational logic solutions

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For a very simple design (like pattern matching, multiplexing or demultiplexing, etc) I'd be happy to use combinational logic straight through. You often see CPLDs used for exactly this purpose.

 

For more complex tasks, what is "possible" and what is "sensible" can be very different. You probably can implement a combinational double-precision floating-point divider - but it's going to be very large (may require a bigger, more expensive chip) and throughout will be low (long paths, no chance for pipelining). A sequential design could well use something like 10% of the resources for 10x the throughput (latency will be larger, but it can be pipelined). In this case it would be sensible to stick with a sequential design.