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Visitor cangyisu
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Registered: ‎06-27-2019

Read digital value into FPGA and display what FPGA gets in txt or excel

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Software: Vivado HLx Editions

FPGA: Artix-7 100T CSG324

Hi, my task is that I want to receive the data from discrete circuit, and that data will only be two levels (digital signal). I want to capture that data in FPGA and export that into a spreadsheet . What should I do? Should I use the pmod ports or XADC ports to get that data? Thank you!

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Scholar u4223374
Scholar
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Registered: ‎04-26-2015

Re: Read digital value into FPGA and display what FPGA gets in txt or excel

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Sorry, missed the rest of your question. In terms of hardware, your block will have four ports:

- Clock in from the 100MHz oscillator on the Nexys A7. Physically this connects to pin E3 on the Artix 7.

- Clock and data in from your data stream (ie the two signals on the oscilloscope). Assuming you're using Pmod port "JA", you can use pins C17 and D18.

- Data out to the UART. The FT2232 USB-UART connects to pin D4 on the Artix 7. You can ignore the three other UART signals.

 

When you plug the USB cable into a PC, you should get a USB composite device showing up, with one UART and one "other" device (the Digilent JTAG port). You just need to open the UART in Tera Term.

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Scholar u4223374
Scholar
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Registered: ‎04-26-2015

Re: Read digital value into FPGA and display what FPGA gets in txt or excel

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For digital data, the Pmod ports are the obvious option (no point using the XADC if you don't need analogue input).

 

To get data back to a PC, most of the development boards include a USB-UART chip. Your design just needs to send the result via a UART, which is trivial (a UART transmitter is just a timer to generate the right frequency, and a shift register). You can read this on the PC with something like Tera Term (free). The easiest approach is probably going to be to have the FPGA output each value followed by a new-line character (0x0A). Log that to a text file with Tera Term, and then Excel should be able to open the logfile.

Visitor cangyisu
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Registered: ‎06-27-2019

Re: Read digital value into FPGA and display what FPGA gets in txt or excel

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Thank you for your reply. I am a beginner in FPGA, so I still have some concerns. Do you mean that I have to write a UART design source (or do I need to do something with the IP catalog?) ? Then what are the inputs and outputs of the module and how should I physically connect these (just connect the "PROG UART" port of FPGA to PC and connect one pin in pmod (because of serial data) to discrete circuits)? What I want is when I inject the signal below (See image) into FPGA, I can get 11110011 in PC. Can you explain more and I really appreciate.1.jpg

 

2.jpg

 

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Scholar u4223374
Scholar
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Registered: ‎04-26-2015

Re: Read digital value into FPGA and display what FPGA gets in txt or excel

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Ah, the oscilloscope photo makes everything clear. That should be pretty straightforward.

First things first, you need to select a baud rate for the UART. The clock you've got is 6kHz (assuming I've done the maths right), and you want to send 10 bits of data from the UART for every clock edge. This requires a minimum of a 60kHz UART clock. Realistically, easiest to use 115.2kHz since that's one of the two most common UART speeds (the other is 9.6kHz).

 

The basic approach is going to be something like this:

(1) Did the input data clock change from low to high since the last FPGA clock cycle (indicating a rising edge)? If not, go to 1 (ie just loop here).

(2) If it did, read the value from the data stream.

(3) If the value is 1, write 000110001 (ASCII for "1") into the UART shift register. Otherwise, write 000110000 (ASCII for '0') into the UART shift register. Note that there's no need to check whether the register is empty; with a 6kHz input clock this is guaranteed - and if it isn't empty, there's not much you can do about it anyway.

(4) Enable the UART timer.

 

Separately:

(1) When enabled, UART timer divides the 100MHz system clock by 868 to get 115200Hz (appropriate for the UART).

(2) Every time the UART timer reaches its threshold (ie one clock tick at 115200bps), the UART shift register shifts left by one space and fills the newly-opened space with a 1.

(3) When the shift register is all 1s, UART timer gets disabled (until it's re-enabled by the next character).

 

There are many ways to do this, but for a quick and dirty approach you can do it all in a single big always@(posedge clk) block (in Verilog).

Scholar u4223374
Scholar
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Registered: ‎04-26-2015

Re: Read digital value into FPGA and display what FPGA gets in txt or excel

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Sorry, missed the rest of your question. In terms of hardware, your block will have four ports:

- Clock in from the 100MHz oscillator on the Nexys A7. Physically this connects to pin E3 on the Artix 7.

- Clock and data in from your data stream (ie the two signals on the oscilloscope). Assuming you're using Pmod port "JA", you can use pins C17 and D18.

- Data out to the UART. The FT2232 USB-UART connects to pin D4 on the Artix 7. You can ignore the three other UART signals.

 

When you plug the USB cable into a PC, you should get a USB composite device showing up, with one UART and one "other" device (the Digilent JTAG port). You just need to open the UART in Tera Term.

Visitor cangyisu
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Registered: ‎06-27-2019

Re: Read digital value into FPGA and display what FPGA gets in txt or excel

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why “send 10 bits of data from the UART for every clock edge”? Is that 8-bit and one start bit and one stop bit?
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Scholar u4223374
Scholar
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Registered: ‎04-26-2015

Re: Read digital value into FPGA and display what FPGA gets in txt or excel

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@cangyisu Yes. 99% of the time a UART byte will be ten bits (start, 8 data bits, stop). Sometimes people use more or less (eg. using longer or shorter data sections, or multiple stop bits, or parity) - but in almost every case you'll find that the settings are "8N1" (8 data bits, no parity, 1 stop bit).

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Visitor cangyisu
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Registered: ‎06-27-2019

Re: Read digital value into FPGA and display what FPGA gets in txt or excel

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I find a verilog code online, would you please review it if it fits your description and what is system clock in this code meaning? Is this the data clock or fpga internal 100MHz clock?

https://excamera.com/sphinx/fpga-uart.html

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