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Explorer
Explorer
20,459 Views
Registered: ‎08-23-2011

Reg: Clock gating for FPGAs ... good or bad?

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hi,

 

i had some queries regarding clock gating.

 

from what i've read/learnt - clock gating can be used for low power fpga designs (switch off the clock to prevent elements from toggling to save power).

 

however, i've also read that clock gating is bad because it can induce glitches into the system. i think i've seen the glitch issue myself. i tried to switch the frequency of a module using a muxed clk which lead to incorrect o/p but using a synchrnous elements (no mux), the design worked fine.

 

so my questions are -

1)should clk gating be there at all in the design?

2)if so, what is the best method for clk gating?

3)is there some good tutorial/UG for efficient(glitch free) implementation technique of clk gating for FPGAs? any links for this will be highly appreciated!

 

Thanks,

Z.

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1 Solution

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Historian
Historian
30,057 Views
Registered: ‎01-23-2009

Re: Reg: Clock gating for FPGAs ... good or bad?

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In ASICs, the clock tree (the set of nets and buffers) that distribute the clock to all clocked elements is built specifically for each device. As a result, it is possible to have clock trees with pretty much any logic in the tree to gate specific clocks or groups of clocks. The clock tree is built to handle all of this, including accomodating the delays through the gating elements.

 

In FPGAs, the clock trees are fixed - they are dedicated nets and buffers responsible for distributing the clock to all elements. It is not possible to do the arbitrary gating that is possible in ASICs.

 

That being said, the FPGA clock tree has certain elements that can be gated. The "root" of the clock tree is the global buffer. It has mutliple personalities from the simplest "BUFG" to the most complicated "BUFGCTRL" (in some architectures). In all architectures, it can have the personality of a BUFGCE. This is a global clock buffer with a clock enable. When used properly (and how depends on which device and which flavor of BUFGCE you use), the BUFGCE can do clock gating glitchlessly. However, in most FPGAs there are only 32 global clock networks - if you want to have multiple gated clocks, each clock uses one of these 32 resources.

 

In addition, in later architectures (Virtex 6 and the 7 series), there are also BUFH cells on the clock tree. These buffers are the connection points between the vertical spines of the 32 global clock nets and the horizontal clock nets that enter each clock region. Like BUFGs, these also have another personality, the BUFHCE. Again, if the CE of these cells is driven synchronously, these cells can gate the clock entering the clock region. There are 12 of these per clock region, so there are many more of them in a device. The restriction is each of these gated clocks can only drive one clock region - hence all logic that uses this gated clock must fit in one clock region.

 

Again, if used correctly, these resources guarantee glitchless clock gating. In addition, if you use ONLY these resources, then all the clocks that start at the same source all arrive at their destinations synchronously - as long as they all go through exactly one BUFG/BUFGCE/BUFGMUX/BUFGCTRL and either zero or one BUFH/BUFHCE. These approaches can be used to reduce system power (by shutting off unnecessary parts of your design), or can also be used for generating decimated clocks.

 

Gating using any other resource, however, is a different story. If you try and gate a clock (say) using a LUT, then the clock needs to leave the clock network, be routed using general routing resources to a LUT, and then be routed back to something that can reach the desired clocks (probably another BUFG or BUFH). It is very difficult to ensure that the clock gated in a LUT is glitch free, and (more importantly) all the extra routing (including the extra BUFG/BUFH) will make this clock arrive later than any clock that stays on the clock tree. The amount of extra delay is variable from place&route run to place&route run, and is also process, voltage and temperature dependent. This kind of gating is NOT recommended in FPGAs.

 

The last point (which was made by another poster) is that each flip-flop within the FPGA has a CE pin. This prevents the updating of the data of the FF. In some cases, you can turn off the updating of some FFs when their value is not needed - this can be done automatically by the tools, and is called intelligent clock gating. By reducing the number of times a FF changes state unecessarily (and hence all the logic driven by that FF), the overall power of the system can also be reduced.

 

I hope this helps.

 

Avrum

4 Replies
Observer ddemmin
Observer
20,456 Views
Registered: ‎02-10-2009

Re: Reg: Clock gating for FPGAs ... good or bad?

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Don't gate the clock (source).  If you are trying to reduce power you should use the clock enable pin on the logic you want to disable.  Alternatively you can use a bufgmux to disable an entire clock net.  For the newer families/tools look at the following white paper.

 

http://www.xilinx.com/support/documentation/white_papers/wp370_Intelligent_Clock_Gating.pdf

Historian
Historian
30,058 Views
Registered: ‎01-23-2009

Re: Reg: Clock gating for FPGAs ... good or bad?

Jump to solution

In ASICs, the clock tree (the set of nets and buffers) that distribute the clock to all clocked elements is built specifically for each device. As a result, it is possible to have clock trees with pretty much any logic in the tree to gate specific clocks or groups of clocks. The clock tree is built to handle all of this, including accomodating the delays through the gating elements.

 

In FPGAs, the clock trees are fixed - they are dedicated nets and buffers responsible for distributing the clock to all elements. It is not possible to do the arbitrary gating that is possible in ASICs.

 

That being said, the FPGA clock tree has certain elements that can be gated. The "root" of the clock tree is the global buffer. It has mutliple personalities from the simplest "BUFG" to the most complicated "BUFGCTRL" (in some architectures). In all architectures, it can have the personality of a BUFGCE. This is a global clock buffer with a clock enable. When used properly (and how depends on which device and which flavor of BUFGCE you use), the BUFGCE can do clock gating glitchlessly. However, in most FPGAs there are only 32 global clock networks - if you want to have multiple gated clocks, each clock uses one of these 32 resources.

 

In addition, in later architectures (Virtex 6 and the 7 series), there are also BUFH cells on the clock tree. These buffers are the connection points between the vertical spines of the 32 global clock nets and the horizontal clock nets that enter each clock region. Like BUFGs, these also have another personality, the BUFHCE. Again, if the CE of these cells is driven synchronously, these cells can gate the clock entering the clock region. There are 12 of these per clock region, so there are many more of them in a device. The restriction is each of these gated clocks can only drive one clock region - hence all logic that uses this gated clock must fit in one clock region.

 

Again, if used correctly, these resources guarantee glitchless clock gating. In addition, if you use ONLY these resources, then all the clocks that start at the same source all arrive at their destinations synchronously - as long as they all go through exactly one BUFG/BUFGCE/BUFGMUX/BUFGCTRL and either zero or one BUFH/BUFHCE. These approaches can be used to reduce system power (by shutting off unnecessary parts of your design), or can also be used for generating decimated clocks.

 

Gating using any other resource, however, is a different story. If you try and gate a clock (say) using a LUT, then the clock needs to leave the clock network, be routed using general routing resources to a LUT, and then be routed back to something that can reach the desired clocks (probably another BUFG or BUFH). It is very difficult to ensure that the clock gated in a LUT is glitch free, and (more importantly) all the extra routing (including the extra BUFG/BUFH) will make this clock arrive later than any clock that stays on the clock tree. The amount of extra delay is variable from place&route run to place&route run, and is also process, voltage and temperature dependent. This kind of gating is NOT recommended in FPGAs.

 

The last point (which was made by another poster) is that each flip-flop within the FPGA has a CE pin. This prevents the updating of the data of the FF. In some cases, you can turn off the updating of some FFs when their value is not needed - this can be done automatically by the tools, and is called intelligent clock gating. By reducing the number of times a FF changes state unecessarily (and hence all the logic driven by that FF), the overall power of the system can also be reduced.

 

I hope this helps.

 

Avrum

Explorer
Explorer
20,425 Views
Registered: ‎09-06-2012

Re: Reg: Clock gating for FPGAs ... good or bad?

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hi

 

Have a  look at this AR http://www.xilinx.com/support/answers/38099.htm for clock gatting.

 

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Explorer
Explorer
20,407 Views
Registered: ‎08-23-2011

Re: Reg: Clock gating for FPGAs ... good or bad?

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thanks for the detailed explanation ... this is what I was looking for! and thank you all for sending links etc .. thanks! :)
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