i have my own pcie controller and i was looking to implement pcie phy on the fpga with a PIPE interface to my controller.
i guess the solution to implemen the PHY on a virtex6 vlx75t fpga is:
>use GTX wizard in coregen and implement the pcie gen2 protocol template to make the core.
my questions are:
1) the gtx core that logicore generates - does it interface with the GTX transcievers on the FPGA board and the entire "gtx core + interface to fpga transcivers" is considered a "PCIe PHY"?
2) i did generate the core for pcie gen2 protocol and i saw some signals in the top level. would these signals be a standard PIPE interface?
3) i noticed that the names of the signals in the xilinx core are a bit different than the PIPE interface signals for an off-the-shelf pcie PHY or PCIe controller. so is there any document (from xilinx) which explains the functionality of the signals generated in the xilinx core so that i know how this would connect to a standard PCIe controller with a PIPE interface?
ive referred to UG516 but it did not have any details of the PIPE interface or PCIe gen2 signals! :(
4) i am still awaiting the controller RTL ... so is there any way of just testing out the PHY part and seeing it works properly? and without using xapp1022?
5) are there some generic pcie drivers already available from xilinx to interface this pcie phy (and my controller) with a host computer? or would they need to be developed specifically?