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cinnamon81
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Registered: ‎09-07-2009

Resource utilization question

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Dear all

 

Quick question about how to make a rough calculation as to the resource utilization of a design.

 

Basically, I'm looking at using a few of the available Xilinx IP cores. In their data sheets, they list resource utilisation for different devices. So to get a (rough) estimate for the total resources used, I simply add them together, correct?

 

Now, as far as I'm aware, a "slice" is simply a number of flip-flops and LUTs. But, according to the number of slices I calculate, my design is too big for my target fpga device. And yet, if I sum the flip-flops, I'm well under the max size for my target fpga. So which number is correct?

 

I don't yet have the development board or software (they are on the way), so I can't syntheisize this yet, but I need to get a rough idea of the resource utilization for my supervisor.

 

Cheers

C

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gszakacs
Instructor
Instructor
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Registered: ‎08-14-2007

LUTs and flip-flops are the basic resources of the FPGA, but they are always packed together

into slices containing some of each.  Depending on what you do with the LUT or flip-flop you may not

be able to use the other resource of the slice.  Usually the slice count is a good first-order indication

for fit because it represents the number of slices the design would use if no non-related logic

is packed into the same slice.  The FPGA can generally hold more logic than this, but when

you exceed this point and start to pack unrelated logic into the same slice, it becomes harder

to meet timing constraints.  You don't need the board to test out the capacity of your device,

just a copy of ISE tools.  If you build a simple project that contains the number of IP cores

you want and has at least a few inputs and outputs to prevent the cores from being optimised

away, you can see whether it will fit or not, and if it does, what sort of timing you might expect.

 

HTH,

Gabor

-- Gabor

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gszakacs
Instructor
Instructor
6,875 Views
Registered: ‎08-14-2007

LUTs and flip-flops are the basic resources of the FPGA, but they are always packed together

into slices containing some of each.  Depending on what you do with the LUT or flip-flop you may not

be able to use the other resource of the slice.  Usually the slice count is a good first-order indication

for fit because it represents the number of slices the design would use if no non-related logic

is packed into the same slice.  The FPGA can generally hold more logic than this, but when

you exceed this point and start to pack unrelated logic into the same slice, it becomes harder

to meet timing constraints.  You don't need the board to test out the capacity of your device,

just a copy of ISE tools.  If you build a simple project that contains the number of IP cores

you want and has at least a few inputs and outputs to prevent the cores from being optimised

away, you can see whether it will fit or not, and if it does, what sort of timing you might expect.

 

HTH,

Gabor

-- Gabor

View solution in original post

cinnamon81
Visitor
Visitor
5,619 Views
Registered: ‎09-07-2009

Thanks, Gabor. That's a great help.

 

I wonder is there any "rule of thumb" for this kind of stuff?

 

For example, is it safe to say that if the total slice count (as per datasheets, rather than synthesis) is above the gate slice count, there's going to be trouble with timing, etc., that make the design infeasible?

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gszakacs
Instructor
Instructor
5,609 Views
Registered: ‎08-14-2007

Well, that's a sort of first-order rule-of-thumb.  In most cases you can do better than the 50% usage

implied by counting occupied slices rather than LUT's and flip-flops.  However there's more work

involved as the design approaches the capacity of the FPGA.  Meeting timing also depends on

how close you come to the FPGA's theoretical maximum performance.  If your design is slow

enough you may not have any problems regardless of placement.  For example suppose your

clock period is larger than a routing delay from corner to corner of the FPGA.   Then unrelated

packing may not cause timing problems at all.  This seems like an extreme case, but it can

happen when using very small but fast parts, like the smallest part in an FPGA family.  Utilizing

100% of the resources in the smallest parts may not be hard at all.  It's a much different story

at the other end of the size spectrum.

 

Regards,

Gabor

-- Gabor
cinnamon81
Visitor
Visitor
5,580 Views
Registered: ‎09-07-2009

Thanks again!

 

One final question on something I've never been quite sure about. What is the relationship between a logic cell and a slice/flip-flop/LUT. (I understand thata slice consists of 4 LUTs and 8 flip-flops inthe Spartan-6 architecture).

 

Cheers

C

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