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Adventurer
Adventurer
6,570 Views
Registered: ‎03-05-2009

Spartan 6 and Cypress CY7C68013A USB component ?

Hello,

 

On a Spartan 6 based board, I need to implement a USB connection.

 

The Cypress CY7C68013A component is said to be a good solution.

I then tried to add the 56 BGA version to my design, but even after having read the datasheets and several internet documentation, I still don't understand how to connect it to the FPGA

 

As only a small amount of data needs to be exchanged between the FPGA and the computer, I would like to avoid using na external FIFO....

 

Do you have any example on how to use this component with a FPGA?

 

Thank you for your help,

 

Alex

 

 

 

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5 Replies
Historian
Historian
6,559 Views
Registered: ‎02-25-2008

Re: Spartan 6 and Cypress CY7C68013A USB component ?


guilvard wrote:

Hello,

 

On a Spartan 6 based board, I need to implement a USB connection.

 

The Cypress CY7C68013A component is said to be a good solution.

I then tried to add the 56 BGA version to my design, but even after having read the datasheets and several internet documentation, I still don't understand how to connect it to the FPGA

 

As only a small amount of data needs to be exchanged between the FPGA and the computer, I would like to avoid using na external FIFO....

 

Do you have any example on how to use this component with a FPGA?

 

Thank you for your help,

 

Alex

 

 

 


The Cypress parts have a "local bus" which is connected to the FPGA.

It's all in the Cypress user guide.

----------------------------Yes, I do this for a living.
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Advisor eilert
Advisor
6,542 Views
Registered: ‎08-14-2007

Re: Spartan 6 and Cypress CY7C68013A USB component ?

 Hi,

See, how others have done it:

 

http://www.cesys.com/resources/ce041_schematics.pdf

 

http://www.cesys.com/resources/CE041.pdf

 

 

It's for a Spartan3, but the same basic design applies to your problem.

 

Have a nice synthesis

  Eilert

 

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Adventurer
Adventurer
6,529 Views
Registered: ‎03-05-2009

Re: Spartan 6 and Cypress CY7C68013A USB component ?

Thank you !

 

It helped me a lot...

 

Some of the signal IO's are connected to the FPGA "System Signals":

 

FX2_PA7 / FLAG 2 <=> FPGA_DONE
FX2_PA4/FIFOADDR0 <=> FPGA_BUSY
FX2_PA5/FIFOADDR1 <=> FPGA_INITB
FX2_PA3/WU2 <=> FPGA_PROGB

 

 

Is it to be able to programm the FPGA using the cypress?

 

Alex

Message Edited by guilvard on 03-12-2010 07:11 AM
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Explorer
Explorer
6,337 Views
Registered: ‎03-25-2010

Re: Spartan 6 and Cypress CY7C68013A USB component ?

I have worked with the FX2, but just with Bulk transfers.

 

Is very easy to use it in Slave Fifo Mode.

 

Here is my VHDL code.

 

Good Luck

 

--------------------------------
--Author: Diego Botero
--delbotero@gmail.com                                                                                                         
--
--------------------------------

library ieee;
use ieee.std_logic_1164.all;


----------------------------------------------------------------------------------------------------
entity FX2_USB is

    port(        reset_n : in std_logic;                        --Reset
                clk : in  std_logic;                    --clk

            -- usb signals
                pktend  : out std_logic;
                sloe : out std_logic;        --Always read data, SLOE always asserted
                slwr  : out std_logic;
                fifo_adr : out std_logic_vector(2 downto 0);    --Endpoints address
                slrd : out std_logic;
                fd : inout std_logic_vector(15 downto 0);    --Data bus
                ifclk : inout std_logic;                    --Clock can be internal or external

            -- Flags
                flag_a: in std_logic;
                flag_b: in std_logic;
                flag_c: in std_logic;
                flag_d: in std_logic;
           
            --User
                --outputs
                data_out : out std_logic_vector(15 downto 0);    --Data out
                flag_read_data : out std_logic;                    --
                --inputs
                data_in : in std_logic_vector(15 downto 0);        --Data in
                flag_write_data : out std_logic                    --

               
                );                    --
           
end FX2_USB;


----------------------------------------------------------------------------------------------------

architecture sintesis of FX2_USB is

begin

----------------------------IFCLK generation---------------------------
PROCESS(clk,reset_n) IS
    VARIABLE status:std_logic;
   
BEGIN
    if reset_n = '0' then
        status    :='0';   
        ifclk<='1';
    elsif clk'EVENT AND clk = '1'THEN   
        if status = '1' then
            status:='0';
            ifclk<='1';
        else
            status:='1';
            ifclk<='0';
        end if;
    end if;

END PROCESS;
       

----------------------------FX2  usb -----------------------------------
PROCESS(ifclk,flag_c,flag_b,reset_n) IS
    VARIABLE status,status2:std_logic;
   
   
BEGIN


pktend  <= '1';        --active low
--+++++++++++++++++++++++++++++++++++++++++++++++++--
if reset_n = '0' then
    sloe <= '1';        --Deassert SLOE
    slrd <= '1';        --Deassert SLRD
    slwr <= '1';        --Deassert SLWR

    fd   <= (OTHERS => 'Z');            --Put the Bus in High Impedance
    flag_write_data <='0';
    flag_read_data<='0';   

        elsIF ifclk'EVENT AND ifclk = '1'THEN   
               
-----------------------------------------------------                 
                IF flag_c = '1' THEN    --usb_flag_c is EP2EF(active low) (EP2EF:Endpoint2 Empty Fifo)
--Read Begin       
                    flag_write_data <='1';
                    flag_read_data<='0';
                    fifo_adr <= B"000";--(OTHERS => '0');    --Select EP2
                    sloe <= '0';        --Always read data, SLOE always asserted
                    slwr <= '1';        --Always read data, SLWR never asserted
                    IF status = '1' THEN
                        slrd <= '0';     --signal asserted ACTIVE LOW
                        status:='0';
                        data_out<=fd;
                    ELSE
                        slrd <= '1';    --signal deasserted ACTIVE LOW
                        status:='1';
                    END IF;
               
--Read End
-----------------------------------------------------
                ELSIF flag_b = '1' THEN    --usb_flag_b is EP6FF(active low) (EP6FF:Endpoint6 Full Fifo)
--Write Begin       
                    flag_write_data <='0';
                    flag_read_data<='1';
                   
                    fifo_adr <= B"010";--(OTHERS => '0');    --Select EP6
                    sloe <= '1';        --Always write data, SLOE never asserted
                    slrd <= '1';        --Always write data, SLRD never asserted
                    IF status = '1' THEN    --status is an internal Variable
                        slwr <= '0';     --signal asserted ACTIVE LOW
                        status:='0';
                    ELSE
                        slwr <= '1';    --signal deasserted ACTIVE LOW
                        status:='1';
                        fd   <= data_in;--usb_fd-1;
                    END IF;
                   
--Write End                           
-----------------------------------------------------                   
                ELSE
                    flag_write_data <='0';
                    flag_read_data<='0';
                    sloe <= '1';        --Deassert SLOE
                    slrd <= '1';        --Deassert SLRD
                    slwr <= '1';        --Deassert SLWR
                    fd   <= (OTHERS => 'Z');    --Put the Bus in High Impedance
               
                END IF;
-----------------------------------------------------           
       
        END IF;--end IF usb_ifclk'EVENT AND usb_ifclk = '1'THEN
--+++++++++++++++++++++++++++++++++++++++++++++++++--

END PROCESS;


end sintesis;

----------------------------------------------------------------------------------------------------

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Adventurer
Adventurer
819 Views
Registered: ‎10-09-2018

Re: Spartan 6 and Cypress CY7C68013A USB component ?

Hello delbotero,

 

You have declared status signal as local variable in two different process block. You are checking and assigning the same variable, also you declared status2 variable but didn't use. Can you please clarify it?

 

Thanks!

--

Regards,

Avinash C

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