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meganadhan
Visitor
Visitor
7,183 Views
Registered: ‎06-25-2014

State Machine design

Dear All,

 

we need to design a state machine having the following behavior

 

MOD 1 :       IDLE -> st1 -> st2 -> st3 -> st4 -> st1 -> st2 -> st3 -> st4 ->st1 -> st2 - - -   and so on.

MOD 2:        IDLE -> st1 -> st2 -> st3 -> st4 -> st5 -> st1 -> st2 -> st3 ->st4 -> st5 -> st1-> st2 -> st3 --- so on

MOD 3 :       IDLE -> st1 -> st2 -> st5 -> st3 -> st4 -> st5 -> st1 -> st2 ->st5 -> st3 -> st4 -> st5 ---- so on

MOD 4 :       IDLE -> st1 -> st5 -> st2 -> st5 -> st3 -> st5 -> st4 ->st5 -> st1 -> st5 -> st2 -> st5 -> st3 -> st5 so on 

 

change from each state depend on a ready signal from a slave(may need to remain in a state until the slave is ready)

 

1. How we can implement this state machine logic with minimum logic (avoid large comparators in each state ) ?

 

Any answers would be greatly appreciated .

 

 

Meganadan

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6 Replies
aher
Xilinx Employee
Xilinx Employee
7,179 Views
Registered: ‎07-21-2014

hi,

 

can you please explain what is mod1, mod2, mod3, mod4?

are you switching between these states depending on some variable?

 

thanks,
Shreyas

 

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meganadhan
Visitor
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Registered: ‎06-25-2014

1. MOD1 and MOD2 are 2 bit inputs to the state machine which need to be checked at IDLE state(frame start) state only

2. State swiching is controlled only by the ready signal from the slave.

3. Once mod is set for a frame it should follow the pattern as shown.

 

Meganadhan

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vijayak
Xilinx Employee
Xilinx Employee
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Registered: ‎10-24-2013

Hi,
Some coding examples are given @ http://www.asic-world.com/tidbits/verilog_fsm.html
Thanks,Vijay
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anusheel
Moderator
Moderator
7,137 Views
Registered: ‎07-21-2014

Hi,

 

Refer below link for FPGA based FSM coding example:

http://www.xilinx.com/support/documentation/university/ISE-Teaching/HDL-Design/14x/Nexys3/Verilog/docs-pdf/lab10.pdf

 

-fsm_extraction is also available in Vivado.

 

Thanks,
Anusheel
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muzaffer
Teacher
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Registered: ‎03-31-2012

make three lookup tables with the sequences you quote, ie for mod 3 {1, 2, 5, 3, 4, 5, -1} where -1 indicates return to index 0 and others indicate next state. have 4 state after idle, one for each mod and have each modx state loop over the ready signal and pick from the respective table. You need to make sure your state machine coding stays current with the contents of the lookup table.
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meganadhan
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Registered: ‎06-25-2014

Hi Muzafir,

 

thanks for your prompt reply.

 

Could u pls elaborate ?

 

Megandhan

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