10-02-2014 08:07 AM
So I have a clock generator module in my Spartan6 design and the module gets the system reset signal. Other modules in the design have synchronous resets and are clocked by the clock generator module. This creates a problem, at least in simulation, that when reset goes high, the clock generator outputs stop. So my other modules have no clock when reset is high, and they don't get reset.
Is this just a simulation artifact or is this what would actually happen in reality? What should I do about it? Thanks!
10-02-2014 08:46 AM
The synchronous reset should be held until a few cycles after the LOCKED signal has been asserted.
10-02-2014 11:17 AM
According to ISIM, the clock generator does not become locked until after you release the reset line.
10-02-2014 12:06 PM
You cannot have the reset pin of the MMCM/PLL controlled by the output of the MMCM/PLL. The control must be independent, sometimes this done using the input to the MMCM/PLL if a seperate control clock is not available.
10-02-2014 12:41 PM
Thanks. We're not saying exactly the same thing, though. I was talking about using the same reset signal for the clock module as the rest of the system. Since the rest of the system uses clocks from the clock module, they will not get synchronously reset because they are not getting clocked, because the clock module is in reset.
I've written a reset module that synchronizes my reset signal to each clock I have and waits until LOCKED goes high before coming out of reset for everything but the clock module.
10-02-2014 02:09 PM
You don't need a synchronous reset for the PLL, DCM or MMCM. And the PLL / MMCM / DCM will not output any clocks while it is held reset as you've already seen in simulation. Using the input clock to run the clocking module's reset state logic is one option, or you could use another unrelated clock, including the internal oscillator on some devices (I've done this in Spartan 6) if you include a STARTUP block in your system.