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Voyager
26,678 Views
Registered: ‎10-25-2012

## The difference between IBUF (IBUFDS) and IBUFG (IBUFGDS)

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There are different buffers in Xilinx FPGA like IBUF, IBUFG, BUFG. I am confused by the difference between them. If someone can help me in following questions that will be great.

1. What is the difference between IBUF (IBUFDS) and IBUFG (IBUFGDS)? Based on my understanding, IBUF is used for data or local clock while IBUFG will be used for global clock. I assume that IBUFDS and IBUFGDS will be same only for differential signals.

2. If I use IBUFG, I still need to connect the output of IBUFG to BUFG, to use it as a global clock in my design, right? (Assume I don't connect the output of IBUFG to MMCM, PLL). I think IBUFGDS will be same only for differential signals.

3. Can I connect the output of IBUF (IBUFDS) to BUFG? If I can and my input to IBUF is a clock signals, is that the output of BUFG a global clock signal?

Thanks in advance.

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Historian
35,743 Views
Registered: ‎02-25-2008

@buddha1987 wrote:

There are different buffers in Xilinx FPGA like IBUF, IBUFG, BUFG. I am confused by the difference between them. If someone can help me in following questions that will be great.

1. What is the difference between IBUF (IBUFDS) and IBUFG (IBUFGDS)? Based on my understanding, IBUF is used for data or local clock while IBUFG will be used for global clock. I assume that IBUFDS and IBUFGDS will be same only for differential signals.

That's correct, except to say that IBUFG/IBUFGDS can only be used on pins which can connect directly to the clock networks. And there's really no such thing as a "local" clock, unless you mean the odd flip-flop which gets its clock from local routing (which is rare). Even the regional clocks and horizontal clocks in FPGA families which have them use an IBUFG for the clock input.

2. If I use IBUFG, I still need to connect the output of IBUFG to BUFG, to use it as a global clock in my design, right? (Assume I don't connect the output of IBUFG to MMCM, PLL). I think IBUFGDS will be same only for differential signals.

Yes, the IBUFG needs to connect to a BUFG (or BUFR or other clock resource). In general, though, you don't need to instantiate either the IBUFG or the BUFG; the tools will infer them.

3. Can I connect the output of IBUF (IBUFDS) to BUFG? If I can and my input to IBUF is a clock signals, is that the output of BUFG a global clock signal?

In generally, you cannot connect the IBUF output to a BUFG. In some FPGA families it's not allowed at all. In others, you'll get a dire warning about "using local routing to connect to clock networks; expect bad timing to result." There's a way to suppress that warning, but generally you shouldn't. The point, of course, is that you always should put clocks onto clock-capable pins, which means doing the FPGA design before committing to a PCB.

----------------------------Yes, I do this for a living.
16 Replies
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Historian
35,744 Views
Registered: ‎02-25-2008

@buddha1987 wrote:

There are different buffers in Xilinx FPGA like IBUF, IBUFG, BUFG. I am confused by the difference between them. If someone can help me in following questions that will be great.

1. What is the difference between IBUF (IBUFDS) and IBUFG (IBUFGDS)? Based on my understanding, IBUF is used for data or local clock while IBUFG will be used for global clock. I assume that IBUFDS and IBUFGDS will be same only for differential signals.

That's correct, except to say that IBUFG/IBUFGDS can only be used on pins which can connect directly to the clock networks. And there's really no such thing as a "local" clock, unless you mean the odd flip-flop which gets its clock from local routing (which is rare). Even the regional clocks and horizontal clocks in FPGA families which have them use an IBUFG for the clock input.

2. If I use IBUFG, I still need to connect the output of IBUFG to BUFG, to use it as a global clock in my design, right? (Assume I don't connect the output of IBUFG to MMCM, PLL). I think IBUFGDS will be same only for differential signals.

Yes, the IBUFG needs to connect to a BUFG (or BUFR or other clock resource). In general, though, you don't need to instantiate either the IBUFG or the BUFG; the tools will infer them.

3. Can I connect the output of IBUF (IBUFDS) to BUFG? If I can and my input to IBUF is a clock signals, is that the output of BUFG a global clock signal?

In generally, you cannot connect the IBUF output to a BUFG. In some FPGA families it's not allowed at all. In others, you'll get a dire warning about "using local routing to connect to clock networks; expect bad timing to result." There's a way to suppress that warning, but generally you shouldn't. The point, of course, is that you always should put clocks onto clock-capable pins, which means doing the FPGA design before committing to a PCB.

----------------------------Yes, I do this for a living.
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Explorer
26,660 Views
Registered: ‎02-22-2010

1) As per UG471 for the 7 series:

"The IBUF and IBUFG primitives are the same. IBUFGs are used when an input buffer is used as a clock input. In the Xilinx tools, an IBUFG is automatically placed at the clock input sites."

The same is valid for IBUFDS and IBUFGDS for differential IO.

Please note that all these primitives are located at the input sites beside the IO pads, contrary to the chip's BUFGs which are located elsewhere.

2) You are right. While the output of IBUFG can be input to a MMCM, it will need to be connected to a BUFG to be distributed as a global clock if no MMCM is used.

3) The connection between IBUF (input pin is not clock capable) and BUFG is NOT recommended since it does not use a dedicated fast path.

Voyager
26,644 Views
Registered: ‎10-25-2012

Thanks very much, both of you.

bassman59, you mentioned this " Yes, the IBUFG needs to connect to a BUFG (or BUFR or other clock resource). In general, though, you don't need to instantiate either the IBUFG or the BUFG; the tools will infer them." Do you mean I don't need to connect IBUFG and BUFG manually?

In my design, I always manually instantiate IBUFG and BUFG, then connect them.

I also post this question for Xilinx application engineer. I got the totally OPPOSITE answers. I put it as following:

If you use IBUF then you need to connect the output of IBUF to BUFG so the clock becomes a global clock output but if you use a IBUFG then the output of IBUFG already is connected to global clock routing resources so no need to to use a BUFG in that case.
You are also wasting global clock resources by using BUFG when you use IBUFG.

Generally, I think he means I don't need BUFG if I use IBUFG. BUFG is only necessay for IBUF.

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Xilinx Employee
26,640 Views
Registered: ‎01-03-2008

> I also post this question for Xilinx application engineer. I got the totally OPPOSITE answers

Please PM me the name of the Xilinx AE that told you this and I will make sure they are re-educated, because they are wrong.

Synthesis will automatically insert a BUFG on clock nets that it detects, but if it already has a BUFG instantiated in the code it will not add another BUFG.  The use of the IBUF vs IBUFG and IBUFDS vs IBUFGDS has not impact on the insertion of a BUFG.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Voyager
26,633 Views
Registered: ‎10-25-2012
Thanks very much mcgett. So generally speaking, I SHOULD manually insert BUFG into my design for clock although Synthesis can do it automatically, right?
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Xilinx Employee
26,629 Views
Registered: ‎01-03-2008

> So generally speaking, I SHOULD manually insert BUFG into my design

It is a personal coding preference.   I create some designs where I need/want explict control for placement and in these designs I insert a BUFG/BUFR/etc so that  I have a known name that I can attach the LOC constraint to.   In most other cases I allowed the synthesizer to do what it is built to do and don't insert a BUFG.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Voyager
26,624 Views
Registered: ‎10-25-2012
Thanks, mcgett. So that looks like the answer from AE is half right, half wrong.

I think he knows that BUFG is unecessay to be put in design by manually. But his statement about "the output of IBUFG already is connected to global clock routing resources so no need to to use a BUFG in that case. You are also wasting global clock resources by using BUFG when you use IBUFG. " is definitely wrong.

IBUFG does not inlcudes BUFG inside it.
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Historian
26,623 Views
Registered: ‎02-25-2008

@buddha1987 wrote:
Thanks very much mcgett. So generally speaking, I SHOULD manually insert BUFG into my design for clock although Synthesis can do it automatically, right?

I generally DO NOT manually insert BUFGs. Synthesis does the right thing.

With Spartan 3E and 3A, I got into the habit of instantiating them not because synthesis wouldn't, but because the mapper was stupid. Say I chose to use a global clock pin GCLK0. If you RTFM, it tells you that there are only a couple of BUFGs to which that pin can directly connect. But when you use it with a DCM, the placer would for whatever reason choose a BUFG on the other side of the chip, then complain that there was no fast connection between the pin and the BUFG. So I would instantiate the BUFG mainly so I would know what it was called and then with that knowledge put a LOC constraint (in the UCF) on that buffer.

----------------------------Yes, I do this for a living.
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Voyager
26,602 Views
Registered: ‎10-25-2012
Thanks very much, bassman59.
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Voyager
13,680 Views
Registered: ‎10-25-2012
Hi mcgett, I just realized I have another question about you states "The use of the IBUF vs IBUFG and IBUFDS vs IBUFGDS has not impact on the insertion of a BUFG."

Do you mean: if Synthesis detects that signals come from IBUF is a clock signal, it will automatically insert a ""BUFG' too in the design?

Thanks.
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Historian
13,677 Views
Registered: ‎02-25-2008

@buddha1987 wrote:

Do you mean: if Synthesis detects that signals come from IBUF is a clock signal, it will automatically insert a ""BUFG' too in the design?

Yes.

i suggest that you spend some time experimenting to see what the synthesis tool does with a given bit of code. Those experiments will likely answer your questions.

----------------------------Yes, I do this for a living.
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Voyager
13,666 Views
Registered: ‎10-25-2012
Thanks very much, bassman59.

I will do some experiments. The thing which confused me is you mentioned "In generally, you cannot connect the IBUF output to a BUFG. In some FPGA families it's not allowed at all. In others, you'll get a dire warning about "using local routing to connect to clock networks; expect bad timing to result."

So that means Synthesis keeps inserting BUFG, it does not care there will be warnings even errors, right?
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Xilinx Employee
13,664 Views
Registered: ‎01-03-2008

> So that means Synthesis keeps inserting BUFG, it does not care there will be warnings even errors, right?

No, what it means is that you did not place the IBUF on a clock capable input that can reach a BUFG.   Every IO should have a LOC and IOSTANDARD set for it.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Voyager
13,654 Views
Registered: ‎10-25-2012
Thanks, mcgett. So now my understanding is: if the signal is inputted through a clock capable input, then NO MATTER I connect it to IBUF or IBUFG, they will be same. Both of them can be connected BUFG, then can be used as a global clock signal, right?
The key is I need input clock through clock capable input, right?

Thanks very much.
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Xilinx Employee
13,650 Views
Registered: ‎01-03-2008

> The key is I need input clock through clock capable input, right?

Yes, you need to place clock inputs on clock capable inputs.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Voyager
13,631 Views
Registered: ‎10-25-2012
Thanks very much, mcgett.