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Explorer
Explorer
9,138 Views
Registered: ‎11-06-2011

Time type problem

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Hey.

 

I've created the following test bench.

 

======================================================================

 

--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:   12:42:38 12/17/2011
-- Design Name:   
-- Module Name:   D:/Work/User_Logic1/Test_Top.vhd
-- Project Name:  User_Logic1
-- Target Device:  
-- Tool versions:  
-- Description:   
--
-- VHDL Test Bench Created by ISE for module: Top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY Test_Top IS
END Test_Top;
 
ARCHITECTURE behavior OF Test_Top IS
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Top
    PORT(
         clk_16_Mhz : IN  std_logic;
         clk_64_Mhz : IN  std_logic;
         Bus2IP_Clk : IN  std_logic;
         Bus2IP_Reset : IN  std_logic;
         Bus2IP_Data : IN  std_logic_vector(0 to 31);
         Bus2IP_BE : IN  std_logic_vector(0 to 3);
         Bus2IP_RdCE : IN  std_logic_vector(0 to 2);
         Bus2IP_WrCE : IN  std_logic_vector(0 to 2);
         IP2Bus_Data : OUT  std_logic_vector(0 to 31);
         IP2Bus_RdAck : OUT  std_logic;
         IP2Bus_WrAck : OUT  std_logic;
         IP2Bus_Error : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clk_16_Mhz : std_logic := '0';
   signal clk_64_Mhz : std_logic := '0';
   signal Bus2IP_Clk : std_logic := '0';
   signal Bus2IP_Reset : std_logic := '0';
   signal Bus2IP_Data : std_logic_vector(0 to 31) := (others => '0');
   signal Bus2IP_BE : std_logic_vector(0 to 3) := (others => '0');
   signal Bus2IP_RdCE : std_logic_vector(0 to 2) := (others => '0');
   signal Bus2IP_WrCE : std_logic_vector(0 to 2) := (others => '0');

     --Outputs
   signal IP2Bus_Data : std_logic_vector(0 to 31);
   signal IP2Bus_RdAck : std_logic;
   signal IP2Bus_WrAck : std_logic;
   signal IP2Bus_Error : std_logic;

   -- Clock period definitions
   constant clk_16_Mhz_period : time := 62.5 ns;
   constant clk_64_Mhz_period : time := 15.625 ns;
   constant Bus2IP_Clk_period : time := 10 ns;
    
    -- Added Signals
    
    type states is (IDLE, SEND, WAIT_ACN);
    signal State_Machine_Write: states;
    signal Do_It_Signal : std_logic;
 
BEGIN
 
    -- Instantiate the Unit Under Test (UUT)
   uut: Top PORT MAP (
          clk_16_Mhz => clk_16_Mhz,
          clk_64_Mhz => clk_64_Mhz,
          Bus2IP_Clk => Bus2IP_Clk,
          Bus2IP_Reset => Bus2IP_Reset,
          Bus2IP_Data => Bus2IP_Data,
          Bus2IP_BE => Bus2IP_BE,
          Bus2IP_RdCE => Bus2IP_RdCE,
          Bus2IP_WrCE => Bus2IP_WrCE,
          IP2Bus_Data => IP2Bus_Data,
          IP2Bus_RdAck => IP2Bus_RdAck,
          IP2Bus_WrAck => IP2Bus_WrAck,
          IP2Bus_Error => IP2Bus_Error
        );

   -- Clock process definitions
   clk_16_Mhz_process :process
   begin
        clk_16_Mhz <= '0';
        wait for clk_16_Mhz_period/2;
        clk_16_Mhz <= '1';
        wait for clk_16_Mhz_period/2;
   end process;
 
   clk_64_Mhz_process :process
   begin
        clk_64_Mhz <= '0';
        wait for clk_64_Mhz_period/2;
        clk_64_Mhz <= '1';
        wait for clk_64_Mhz_period/2;
   end process;
 
   Bus2IP_Clk_process :process
   begin
        Bus2IP_Clk <= '0';
        wait for Bus2IP_Clk_period/2;
        Bus2IP_Clk <= '1';
        wait for Bus2IP_Clk_period/2;
   end process;
 
    PLB_proc : process( Bus2IP_Clk ) is
  begin

    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
      if Bus2IP_Reset = '1' then
        
            Bus2IP_Data <= (others => '0');
            Bus2IP_BE <= "0000";
            Bus2IP_WrCE <= "000";
            Bus2IP_RdCE <= "000";
            State_Machine_Write <= IDLE;
        
      else
            
            case State_Machine_Write is
                
                when IDLE =>
                    
                    if (Do_It_Signal = '1') then
                        
                        State_Machine_Write <= SEND;
                    
                    else null;
                    end if;
                
                when SEND =>
                    
                    Bus2IP_Data <= x"DEADBEEF";
                    Bus2IP_BE <= "1111";
                    Bus2IP_WrCE <= "010";
                    Bus2IP_RdCE <= "000";
                    State_Machine_Write <= WAIT_ACN;
                
                when WAIT_ACN =>
                    
                    if (IP2Bus_WrAck = '1') then
                        
                        Bus2IP_Data <= x"DEADBEEF";
                        Bus2IP_BE <= "0000";
                        Bus2IP_WrCE <= "000";
                        Bus2IP_RdCE <= "000";
                        State_Machine_Write <= IDLE;
                    
                    else null;
                    end if;
                
                when others => null;
            
            end case;
        
        end if;
    
     else null;
     end if;

  end process;
    
            
   -- Stimulus process
   stim_proc: process
   begin        
      -- hold reset state for 100 ns.
        Bus2IP_Reset <= '0';
      wait for Bus2IP_Clk*10.5;    
        Bus2IP_Reset <= '1';
        Do_It_Signal <= '0';
      wait for Bus2IP_Clk*10;
        Bus2IP_Reset <= '0';
      -- insert stimulus here
        
        Do_It_Signal <= '1';
        
        wait for Bus2IP_Clk;
        
        Do_It_Signal <= '0';
        
      wait;
   end process;

END;

 

======================================================================

 

I get the following errors

 

======================================================================

 

ERROR:HDLCompiler:9 - "D:/Work/User_Logic1/Test_Top.vhd" Line 193: Found 0 definitions for operator "*".
ERROR:HDLCompiler:9 - "D:/Work/User_Logic1/Test_Top.vhd" Line 196: Found 0 definitions for operator "*".
ERROR:HDLCompiler:841 - "D:/Work/User_Logic1/Test_Top.vhd" Line 202: Expecting type time for <bus2ip_clk>.
ERROR:HDLCompiler:854 - "D:/Work/User_Logic1/Test_Top.vhd" Line 38: Unit <behavior> ignored due to previous errors.

 

======================================================================

 

It doesn't recognize bus2ip_clk as a type time for some reason.

 

When I use clk_16_Mhz, it does works.

 

Any idea guys?

 

Thanks a lot.

 

Assaf.

 

 

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1 Solution

Accepted Solutions
Advisor joelby
Advisor
11,603 Views
Registered: ‎10-05-2010

Re: Time type problem

Jump to solution

I don't know much VHDL, but it looks like you're not using "wait for" correctly.

 

"wait for" usually accepts a parameter in seconds, not a signal. If you want to wait for a clock edge, use "wait until rising_edge(clk)". 

 

If you want to wait for multiple clock periods, you could do

for i in 1 to 10 loop
    wait until rising_edge(clk);
end loop;

Note that you can't wait for half a clock cycle by doing * 10.5 (unless the thing you're multiplying is a constant that represents the clock period). The simulation tool doesn't know when half a clock period has elapsed because it only knows about edges. Consider what would happen if your duty cycle or period varied over time.

 

Of course you can wait for a rising edge and then wait for the subsequent falling edge, or use the "wait for Clock_Period;" method.

 

In addition to reading your VHDL textbook, I can recommend XAPP199 Writing Efficient Testbenches.

 

View solution in original post

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16 Replies
Instructor
Instructor
9,137 Views
Registered: ‎07-21-2009

Learning VHDL

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Have you yet purchased and read a VHDL primer or study book?  How far in your VHDL self-teaching have you progressed?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Highlighted
Explorer
Explorer
9,132 Views
Registered: ‎11-06-2011

Re: Time type problem

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Hey.

Well, I'm working all day...I don't have time to stop and read a book, I'm learning on the fly.


I wish I would due...


Anyway, do you know what may be the problem?


Thanks a lot.


Assaf
Tags (2)
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Advisor joelby
Advisor
11,604 Views
Registered: ‎10-05-2010

Re: Time type problem

Jump to solution

I don't know much VHDL, but it looks like you're not using "wait for" correctly.

 

"wait for" usually accepts a parameter in seconds, not a signal. If you want to wait for a clock edge, use "wait until rising_edge(clk)". 

 

If you want to wait for multiple clock periods, you could do

for i in 1 to 10 loop
    wait until rising_edge(clk);
end loop;

Note that you can't wait for half a clock cycle by doing * 10.5 (unless the thing you're multiplying is a constant that represents the clock period). The simulation tool doesn't know when half a clock period has elapsed because it only knows about edges. Consider what would happen if your duty cycle or period varied over time.

 

Of course you can wait for a rising edge and then wait for the subsequent falling edge, or use the "wait for Clock_Period;" method.

 

In addition to reading your VHDL textbook, I can recommend XAPP199 Writing Efficient Testbenches.

 

View solution in original post

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Explorer
Explorer
9,094 Views
Registered: ‎11-06-2011

Re: Time type problem

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Oh, you are right.

 

I waited on the clock itself instead of the constant which I created the clock with.

 

Thanks a lot.

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Historian
Historian
9,075 Views
Registered: ‎02-25-2008

Re: Time type problem

Jump to solution

@assaf_malki wrote:
Hey.

Well, I'm working all day...I don't have time to stop and read a book, I'm learning on the fly.

Then I don't have time to read your uncommented code to help you.

----------------------------Yes, I do this for a living.
Explorer
Explorer
9,073 Views
Registered: ‎11-06-2011

Re: Time type problem

Jump to solution

I think it came out wrong.

 

It's not like I don't want to.

 

It's just that I'm working from 8:00 to 20:00 (new job + graduate), I don't have that option to stop and open a book...

 

Thanks.

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Historian
Historian
9,068 Views
Registered: ‎02-25-2008

Re: Time type problem

Jump to solution

@assaf_malki wrote:

I think it came out wrong.

 

It's not like I don't want to.

 

It's just that I'm working from 8:00 to 20:00 (new job + graduate), I don't have that option to stop and open a book...

 

Thanks.


That sound you hear is the World's Smallest Violin playing "My Heart Bleeds For You." 

Really, it's not like the rest of us don't work full time and have kids and all of the other things that might preclude spending an hour of quality time an evening with a dry textbook ...

----------------------------Yes, I do this for a living.
Instructor
Instructor
9,060 Views
Registered: ‎07-21-2009

Re: Time type problem

Jump to solution

I think it came out wrong.

 

No, it didn't.

 

It's not like I don't want to.

 

This is a fine distinction.

 

Your company hired you, an inexperienced and untrained designer, to design a product which requires extensive experience and training.  A choice was made to spend less money for hiring you, an unqualified employee, and your employer is using the volounteer correspondents in these forums to provide training and design expertise for which your employer invests no money or effort other than your personal stress and unsustainable and unhealthy lifestyle.

 

In other words, you (and the forum folks) are being exploited by your employer.  And you are a willing player.

 

The purpose of these forums is -- primarily -- to aid current and prospective Xilinx customers in the use of Xilinx products.  These forums were intended for the purposes of being exploited -- providing useful support without expectation of compensation.

 

If you don't think you are exploiting these forums, consider that you have recorded 90 posts in less than two months' time.  Consider all the time and effort spent reading and responding to your posts.

 

As part of a volounteer group of disorganised correspondents, I stand by my recommendation that you seek proper training.  In very short time, the investment in time and money will have been justified several times over.

 

Agreeing with the thoughts and sentiments which bassman expressed, I prefer to help those who need help rather than those who choose not to help themselves.  You don't need our help, you've simply decided that we're a cheaper and more expedient short-term solution than real training, and your time (and your employer's money) is worth more to you than our time and money.  If you can continue with this approach, I wish you well, and bid you adieu.

 

You are undoubtedly a very quick learner with a good mind for engineering.  I have no doubt that you will succeed in whatever endeavours you undertake.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Explorer
Explorer
9,052 Views
Registered: ‎11-06-2011

Re: Time type problem

Jump to solution

@eteam00 wrote:

I think it came out wrong.

 

No, it didn't.



I don't want people to think that I don't want to learn and ask for your help out of laziness, this is not the case.

 

I really have a great appreciation for all of you guys and if you think that I don't try to find the solution for my self before posting a question here, then you are wrong.

 

Sorry if I ask too much newbie question, It's probably because I'm one...

 

Anyway, I'm very pleased with what I'm doing, I'm learning so much and it's a lot becuase of you guys.

 

So thanks and



You are undoubtedly a very quick learner with a good mind for engineering.  I have no doubt that you will succeed in whatever endeavours you undertake.

 

-- Bob Elkind


Thanks.

 

Assaf.

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Instructor
Instructor
6,660 Views
Registered: ‎07-21-2009

Re: Time type problem

Jump to solution

I really have a great appreciation for all of you guys and if you think that I don't try to find the solution for my self before posting a question here, then you are wrong.

 

No, we're not wrong.  In the course of one recent thread:

  • You haven't tried to take a course in VHDL or taken time to properly study a VHDL primer.
  • You didn't bother to study DRAM speed testing.
  • You didn't bother to learn IIC or SPD.
  • You didn't bother to read an SDRAM SODIMM datasheet for SPD information.
  • You posted several versions of C code snippets for review, absent the most minimal hardware troubleshooting (UCF problem)
  • etc. etc. etc.

Am I mistaken?

I'm sure you do a tremendous amount of learning and research during the day, away from this forum -- but saying that you try as much as possible to be self-sufficient would be -- at best -- an incomplete characterisation.

 

Sorry if I ask too much newbie question, It's probably because I'm one...

 

Sorry, no sympathy from me.  You're smart enough to learn on your own in many cases, but you have often relied on others to do your grunt work, for which you are 'too busy'.

 

Anyway, I'm very pleased with what I'm doing, I'm learning so much and it's a lot because of you guys.

 

Thanks for the acknowledgment.  Let's see if you take the time to return the favour by helping others learn from your investment of time and effort.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
6,643 Views
Registered: ‎07-06-2008

Re: Time type problem

Jump to solution

@assaf_malki wrote:

I think it came out wrong.

 

It's not like I don't want to.

 

It's just that I'm working from 8:00 to 20:00 (new job + graduate), I don't have that option to stop and open a book...

 

Thanks.



What exactly has your boss told you? Is it something along the lines of "Just get it done within x days, I don't care how you do it or that you don't have enough experience etc."

If that is the case, your boss is probably one of those "wannabe managers/aspiring entrepreneurs" who

 

a) Don't have a clue as to how these things work, and they pretend to know that they do.

b) Think that inexperienced and young people can be bullied/pressured/intimidated to do the boss' bidding.

 

Such people are difficult to deal with, and its difficult to make them see the reality. I know, because I have had the misfortune of working under such a moron. My solution: I switched jobs the moment I secured another one.

The guys above me have nailed it, you should trust them, in my opinion. You need to equip yourself properly before you venture in this field. Otherwise, you can continue trying to please your boss and fooling yourself that you are actually learning something in the process. Overtime, you will learn how to do things, but the progress would be very slow and there is a high probability of there still being gaping holes in your education, and when you get stuck doing something that you haven't encountered before, you will get very frustrated.

Historian
Historian
6,619 Views
Registered: ‎02-25-2008

Re: Time type problem

Jump to solution

@eteam00 wrote:

 

Your company hired you, an inexperienced and untrained designer, to design a product which requires extensive experience and training.  A choice was made to spend less money for hiring you, an unqualified employee, and your employer is using the volounteer correspondents in these forums to provide training and design expertise for which your employer invests no money or effort other than your personal stress and unsustainable and unhealthy lifestyle.


My 2,000-mile view is that our new friend works for one of those offshore (at least, off of the shores of the US) companies that provides outsourced designs to clients who don't know, or don't want to know, any better. It is no surprise that the offshore design mill would hire the least-qualified people to do these jobs, because as we all know, labor costs cut into profit, and we can't have reduced profit.

 

I kinda feel sorry for the guy, as it's obvious he wants to be a design engineer, but the only opportunities available to him are these design mills.

----------------------------Yes, I do this for a living.
Explorer
Explorer
6,612 Views
Registered: ‎11-06-2011

Re: Time type problem

Jump to solution

@bassman59 wrote:

@eteam00 wrote:

 

Your company hired you, an inexperienced and untrained designer, to design a product which requires extensive experience and training.  A choice was made to spend less money for hiring you, an unqualified employee, and your employer is using the volounteer correspondents in these forums to provide training and design expertise for which your employer invests no money or effort other than your personal stress and unsustainable and unhealthy lifestyle.


My 2,000-mile view is that our new friend works for one of those offshore (at least, off of the shores of the US) companies that provides outsourced designs to clients who don't know, or don't want to know, any better. It is no surprise that the offshore design mill would hire the least-qualified people to do these jobs, because as we all know, labor costs cut into profit, and we can't have reduced profit.

 

I kinda feel sorry for the guy, as it's obvious he wants to be a design engineer, but the only opportunities available to him are these design mills.


So wrong :)

 

Have a good day.

 

Assaf.

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Instructor
Instructor
6,603 Views
Registered: ‎07-21-2009

Re: Time type problem

Jump to solution

So wrong :smileyhappy:

 

Have a good day.

 

Assaf.

 

Please don't be mad at us, Assaf.  We're not trying to beat up on you.  It's more that we have genuine concern for you, a recent college grad with little professional experience -- that your employer is taking advantage of your hopes and lofty goals and aspirations.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Explorer
Explorer
6,591 Views
Registered: ‎11-06-2011

Re: Time type problem

Jump to solution

@eteam00 wrote:

So wrong :smileyhappy:

 

Have a good day.

 

Assaf.

 

Please don't be mad at us, Assaf.  We're not trying to beat up on you.  It's more that we have genuine concern for you, a recent college grad with little professional experience -- that your employer is taking advantage of your hopes and lofty goals and aspirations.

 

-- Bob Elkind


Try no professional experience at all... :)

 

Anyway, you may see it this way.

 

I see it as a great opportunity for me, I have here a great platform to learn.

 

BTW I'm from Israel, not a lot of company's here are willing to take a recent college grad and give him this option.

 

It's not easy to find a job in R&D in here and that's way I'm grateful.

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Instructor
Instructor
6,588 Views
Registered: ‎07-21-2009

Re: Time type problem

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not a lot of company's here are willing to take a recent college grad and give him this option.

 

What's the option?

 

It's not easy to find a job in R&D in here and that's why I'm grateful.

 

Be careful what you wish for... you may get it.

 

Does your employer plan to use you until you burn out from long hours, no support, and eventual frustration?  Or does you employer plan to guide you and support you by continuing your education and imposing reasonable and achievable expectations (deadlines, technical objectives, project overhead) for your work?

 

Life -- and design projects -- are marathons.  It matters little who sprints fastest from the starting line, and matters greatly who finishes first at the finish line.  Only the runner who establishes a steady and maintainable pace will finish.  Here in the USA we have a word for design engineers who burn out in their work: farmers (just kidding).

 

So... have you had a conversation with your project manager about what help you need -- training, guidance, tools, deadlines, additional manpower -- to successfully complete your project?

 

I spent the first two years of my engineering career working 16-hour days, with almost no social life, and barely caring for myself.  My employer tried to discourage me from this sort of self-destructive and short-sighted lifestyle, and my employer was right.  Along the way, my employer gave me every opportunity to learn from very experienced people.  And my employer made sure that my naive and unrealistic schedule projections were ignored -- and replaced with realistic deadlines and objectives.  That's probably why I'm still an engineer and not a farmer.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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