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3,284 Views
Registered: ‎07-25-2014

Trying to create a digital filter in a CPLD

I'm working on a project where a "somewhat" time sensitive series of pulses passes through a CPLD to turn on/off an IR LED.  the input signal looks like this; An input "trigger" signal has a series of 4 pulses (rising edge) that are 1.52ms high, then 1.36ms low (4 times), followed by a 14.5ms low "quiet time" and then the process repeats.  The problem is that during the "high" phase of each pulse there is noise with sufficient amplitude to cause false transistions high/low.

 

I want to recreate this pulse train and only use the rising edge of the "initial" input trigger signal edge, then send out my own internally generated high=1.52ms -> low=1.36ms for 4x then stop low, ignoring any new input triggers during the 10.3ms duration it takes to pump out this series of 4 pulses, then wait for the next "good" rising edge after a 5ms "block out" period (this allows the input trigger signal time enough to get quiet).

 

I'd appreciate any ideas.

 

Thanks

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Xilinx Employee
Xilinx Employee
3,272 Views
Registered: ‎07-31-2012

Hi,

 

There is no clock module inside the CPLD to control the high low time. you need to use an FPGA with an MMCM/PLL module to do such duty cycle control.

Thanks,
Anirudh

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Xilinx Employee
Xilinx Employee
3,271 Views
Registered: ‎07-31-2012

Hi,

 

Check this AR to know how to divide clock but nothing on the duty cycle. -http://www.xilinx.com/support/answers/21200.html

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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Highlighted
3,254 Views
Registered: ‎07-25-2014

Switching to an FPGA is a design change and not possible.  Besides, I already have the duty cycle worked out and can recreate the pulse timing on my own in the CPLD using the 8MHz input clock as a clock source.    The question is, how to do I kick this off with a non-retrigerable one shot?

 

Thanks

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