04-20-2011 12:47 AM
I want to implement a two dimensional array (memory) in VHDL, and want to access (read ) it through various components, one of the components (both for reading and writing)is in verilog.
Can anyone suggest me a way to declare a module and its linkage to various components.
04-20-2011 02:22 AM
04-20-2011 08:41 AM
04-20-2011 09:12 AM
what is your experiance in vhdl ?
can you write a single vector module ?
04-20-2011 03:04 PM
VHDL probably allows you to have two dimensional arrays in the component's ports.
Verilog does not allow multidimensional arrays in ports.
So the usual method is to define a two-dimensional array that behaves just like
distributed or block RAM (depending on how big it is and how it's used), possibly
multiported. Then run the address and data ports (not the array itself) of the
RAM to the module ports.
It doesn't really matter whether the module containing the RAM is VHDL or Verilog. The
important point is to have all of the behavioral code for memory access (the address
and data ports, and read and write processes) in the module where the memory
is defined. You can get this from the language templates or the XST manual.
04-20-2011 10:07 PM
04-21-2011 02:44 AM
04-21-2011 05:31 AM
Dear users, I am new to FPGAs. I have made some programs in verilog. VHDL I am trying for the first time. My concern is how can we bring the memory to entity port? That too has to be used as input (many components) and output(for one comp, for writing purpose). In verilog I was able to access the memory simply as reg1<=memory[address]; that too inside a single module. I am confused how to bring this memory at port, there may be too many wires to connect to diff modules/entity. Again I can go for declare as many vectors/reg as memory elements, but the problem is same how to bring them all at the port? Please provide me a direction. Pras
This is really a hardware design issue, not a language issue. If you don't want synthesis to
generate thousands of flip-flops to build your "memory" you need to abide by the rules of the
available memory structures (single or dual port, distributed or block RAM). The memory itself
should always be contained within one module (or component). That module needs to have
all of the direct access to the memory array as in reg1<=memory[address]; The ports
of the module are the ports of the memory (addr_a, addr_b, din_a, din_b, dout_a, dout_b ...)
not the memory array itself.
As I said in the earlier post, you can find VHDL (or Verilog) templates for inference of
all available memory types in the language templates as well as the XST user manual.
So the short answer of how to attach the memory array to module (component) ports is
don't do it. While it is allowed in VHDL, you can't access it from Verilog, and the synthesis
tools will not infer memory, but rather tons of flip-flops.
04-23-2011 02:40 AM
04-23-2011 03:35 AM
I'm going to be blunt here,
you are way off base. way way off base.
don't mix languages, that is true, but that is not the basic feature,
it's that you are not experianced enough in vhdl / verilog,
and you seem to be approaching a description language in the same way
you would a stack process like C++.
you need to take step back me thinks,
04-23-2011 07:21 PM
> I wrote a vhdl programme to write and read memory. I did it successfully.
Actually, you created a VHDL design. You are not creating "programs" you are creating a hardware design.
> Then I added this vhdl file as a component to another verilog program.
Actually, you added the VHDL design as a component or sub-module in another Verilog design.
> I tried to acces theis vhdl component using address and data lines.
You are creating hardware and not software, so you are not accessing the VHDL read/write memory design that you created earlier. The Verilog design would be controlling the VHDL design by providing the necessary hardware signals for address, data and clock and in return using the data output in other parts of the Verilog design.
> But during synthesis it displayed error of multisourcing on the data signal. Though this data signal is
> output of the vhdl programme and is being used as an input only.
When the synthesizer reports that a net has multiple sources it means that you have two points in your HDL that are trying to change the state of the net. You will need to re-examine your HDL source to determine where this occuring.
My guess is that this is occuring because you are trying to do something that is not practical in a real design. Way back at the beginning of this thread you stated that you wanted to have a single two dimensional memory array that can be accessed from many places within the design. This concept works with software running on a CPU, but you are not designing software you are designing hardware.
The hardware that you are creating runs everything circuit at the same time time, while software runs each instruction sequentially. If you have 10 modules that each want to read or write the memory array then that means that you need a 10 port memory. Creating a 10 port memory is not practical in an FPGA, but can be done if needed. You will need to create a memory module that has 10 ports each with address, data_in, data_out and read/write in order to do this.
> Is this problem due to the mixing of verilog and vhdl.
No it is because your design is wrong.