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vishalk
Visitor
Visitor
7,911 Views
Registered: ‎11-28-2011

Using Clocks with uneven duty cycle(10% on , 90%off) in synchronous design.

hi,

      Is it feasible to use clocks with uneven duty cycle in synchronous designs, i am using these clocks to perform operations on rising edge and falling edge. I am using these pulses as clocks in always blocks . Please suggest.

 

thanks,

vishal

 

 

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15 Replies
eilert
Teacher
Teacher
7,908 Views
Registered: ‎08-14-2007

Hi Vishal,

mainly there are two possibilities when one writes about using both clock edges.

1) Someone with a high understanding of FPGA technologie using this method wisely when benefitial.

2) Someone with some cunning ideas and a tendency to mess up a design due to a lack of understanding the principles of synchronous design.

 

DCMs and other clock sources in general only create 50% duty cycle signals. One reason is that they are also able to generate phase locked shifted signals on 90, 180, and 270 degrees, for special purposes.

If you happen to generate a 10% duty cycle clock somehow, you need to get it on some global clock net. Otherwise skew effects would mess up your design function.

 

Having only 10 % duty cycle and processes triggering on both clock edges results in som paths that allow only for a very small delay (unless the clock frequency is somewhat low). This can cause trouble for timing closure.

 

I'm already assuming that you have multiple processes triggerd like this:

  always @(posedge clk)

      ...

  always @(negedge clk)

     ...

because

  always @(clk)

wouldn't work in synthesis. FPGAs just don't have DDR-FFs (except for I/O purposes)

 

What's your special design that would require such a strange clocking scheme?

 

Have a nice synthesis

  Eilert

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vishalk
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Registered: ‎11-28-2011

hi  Eilert,

                 Thanks for the suggestion, I am using these uneven clock sources because the data from the previous stage is available according to that clock, instead can i use this pulse(uneven clock) as condition to perform my operations with master clock as reference in always block.

 

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rcingham
Teacher
Teacher
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Registered: ‎09-09-2010

How fast is this clock?

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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eteam00
Instructor
Instructor
7,897 Views
Registered: ‎07-21-2009

I am using these uneven clock sources because the data from the previous stage is available according to that clock, instead can i use this pulse(uneven clock) as condition to perform my operations with master clock as reference in always block.

 

Please be more specific.  There are a number of timing attributes of clocks, please note which attributes apply.

 

Are input data sourced from a common timebase or not?

Are input data phase aligned or not?  Or does phase alignment of input data change (variable skew)?

 

There are clock/data de-skewing capabilities which vary between the FPGA families.  Do you have a specific device target in mind?

 

Is this a theoretical or academic design as part of a school project or thesis, or is this a commercial design which must be realised and operational?

 

Bottom line:  please describe the nature and cause of the apparent timing misalignment of the various input data.

 

-- Bob Elkind

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vishalk
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Registered: ‎11-28-2011

thanks bob,

                       its a valid signal indicating data is valid only when signal is high , for processing it in next stages i am using it has clock source for the next module. On general note i want to know whether it is right to use a clock with uneven duty cycle in always block and perform edge operations on it.

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eteam00
Instructor
Instructor
7,886 Views
Registered: ‎07-21-2009

I did not understand your response.  Did you understand my (previously posted) questions?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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eilert
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Teacher
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Registered: ‎08-14-2007

Hi,

from the few things you have written now I'm suspecting that you are going to do something nasty in your design.

(using some slightly delayed DataValid signal to clock some consecutive circuit stage...gives me a shiver down my spine)

 

Maybe if you provide a little code example we can understand better and explicitly give you comments on your design.

 

Have a nice synthesis

  Eilert

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eteam00
Instructor
Instructor
7,878 Views
Registered: ‎07-21-2009

using some slightly delayed DataValid signal to clock some consecutive circuit stage...gives me a shiver down my spine

 

Does eilert understand your intentions correctly?  If so, why wasn't this stated in the very first post in this thread?

 

If this is indeed the case, this discussion should be scrapped and re-started.

Here is a basic starting point for discussion:

 

1.  What are your input signals

2.  What is your system clock (and how does it relate to the input signals)

3.  What are you trying to achieve

4.  Is this a teaching course exercise, or do you have a specific product design in mind?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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vishalk
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Registered: ‎11-28-2011

here is the code snippet,

 

  always @(negedge valid_out_new or negedge ASYNC_RESET)
           begin
            if(!ASYNC_RESET)
                begin
                 energy2_1  <=  28'd0;  
                 best_tm <= 3'd0;      
               end
            else
            if(best_tm_valid_fin)
                begin
                 energy2_1  <=  28'd0;
                  best_tm <= best_tm;
                end
            else
            if(((Avgiqsq[timing_index_valid])> energy2))
                 begin
                   energy2_1<=(Avgiqsq[timing_index_valid]);
                   best_tm<=i_new;
                end
          end
here valid_out_new has 10% on cycle and 90% off cycle

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eteam00
Instructor
Instructor
5,095 Views
Registered: ‎07-21-2009

Please provide some explanation of what function your code snippet is intended to implement.

 

Also:

1.  What is data input bit-rate.

2.  What is internal (FPGA) logic system clock frequency

3.  What is pulse width of the VALID input signal

 

I will ask this once, and then leave you alone on the matter:  Are you really so brilliant and capable that you have no need for comments in your code?

 

-- Bob Elkind

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Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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eilert
Teacher
Teacher
5,090 Views
Registered: ‎08-14-2007

Hi,

Bob is right, this code snippet is useless without additional information.

This always block for itself is ok, no matter what the duty cycle of the valid_out_new signal is.

But...

The questionable point is wether this signal is your only clock signal (and routed over a clock net) or, if you have other clocks for other always blocks, how is the relation between these clocks. (And how are you dealing with data transfer between clock domains).

And of course the frequency of your clocks would be interesting.

 

Besides, do you know about the concept of pipelining in a synchronous design?

 

Have a nice synthesis

  Eilert

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rcingham
Teacher
Teacher
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Registered: ‎09-09-2010

"here is the code snippet"

I'm glad it is in Verilog so that I do not understand the full horror of it!

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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bassman59
Historian
Historian
5,081 Views
Registered: ‎02-25-2008


@vishalk wrote:

here is the code snippet,

 

@  always @(negedge valid_out_new or negedge ASYNC_RESET)
           begin
            if(!ASYNC_RESET)
                begin
                 energy2_1  <=  28'd0;  
                 best_tm <= 3'd0;      
               end
            else
            if(best_tm_valid_fin)
                begin
                 energy2_1  <=  28'd0;
                  best_tm <= best_tm;
                end
            else
            if(((Avgiqsq[timing_index_valid])> energy2))
                 begin
                   energy2_1<=(Avgiqsq[timing_index_valid]);
                   best_tm<=i_new;
                end
          end
here valid_out_new has 10% on cycle and 90% off cycle


Wow, that code is crap. I am serious. It's sensitive to the falling edge of valid_out_new, yet the process does nothing with that signal.

----------------------------Yes, I do this for a living.
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bassman59
Historian
Historian
5,080 Views
Registered: ‎02-25-2008


@vishalk wrote:

hi,

      Is it feasible to use clocks with uneven duty cycle in synchronous designs, i am using these clocks to perform operations on rising edge and falling edge. I am using these pulses as clocks in always blocks . Please suggest.

 

thanks,

vishal

 

 


To answer this specific question: yes, you can. However, you don't want to use such a clock if you need to use both edges. Why? Because the duty cycle also directly sets the maximum allowable logic delay between the opposite edges of the clock.

 

Consider a 100 MHz clock with a 10% duty cycle. This implies a 10 ns clock period between two rising or two falling edges. But 10% of 10 ns is 1 ns (which is the on time). Now, think: what is the time between a rising edge and the next falling edge? Yes, you are right, it is 1 ns. That means that the allowable time for logic to propagate from the tCO after the rising edge of the clock to the setup before the falling edge is 1 ns. This is the same period as for a 1 GHz clock! Do you think your FPGA is that fast?

----------------------------Yes, I do this for a living.
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eteam00
Instructor
Instructor
5,077 Views
Registered: ‎07-21-2009

Wow, that code is crap. I am serious. It's sensitive to the falling edge of valid_out_new, yet the process does nothing with that signal.

 

Too harsh.  Valid_out_new input signal is used as a clock for this process.  There is no technical fault with this coding, it closely follows the ISE template for a D-FF with negedge clock and async active low reset.  The real issues are more general and conceptual.

 

Vishalk is a valued future Xilinx customer, let's give vishalk a chance before we drive him/her away.  We've helped folks with much less coding proficiency before.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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