Hi,
I used System Generator to make a small model and to export it as a ngc netlist.
Then, with Platform Studio, I created a peripheral for the PLBv4.6 bus.
In the user_logic.vhd file, I instanciated the component created with sysgen.
When I try to generate the bitstream, I have this error:
ERROR:NgdBuild:604 - logical block 'adderngc_0/adderngc_0/USER_LOGIC_I/Addition'
with type 'testngcise_cw' could not be resolved. A pin name misspelling can
cause this, a missing edif or ngc file, or the misspelling of a type name.
Symbol 'testngcise_cw' is not supported in target 'virtex4'.
It's weird, I've done like other people on the forum said, adding OPTION STYLE = MIX in the .mbd file, putting my .ngc in the netlist folder.
